CHL8505 Datasheet, PDF (13/15 Pages) International Rectifier – High.Efficiency 5V MOSFET Gate Driver

High‐Efficiency 5V MOSFET Gate Driver _CHL8505
APPLICATION INFORMATION
BOOT STRAP CIRCUIT
Once the high‐side MOSFET selection is made, the
bootstrap circuit can be defined. The integrated boot
diode of the CHL8505 reduces the external component
count for use in cost and space sensitive designs. For ultra
high efficiency designs, an external boot strap diode is
recommended.
The bootstrap capacitor C_Boot stores the charge and
provides the voltage required to drive the external high‐
side MOSFET gate. The minimum capacitor value can be
defined by:
C_Boot = Q_{HS MOSFET_gate} / ∆V_Boot
where,
 Q_{HS MOSFET_gate} is the total gate charge of the
high‐side external MOSFET(s)
 ∆V_Boot is the droop allowed on the boot capacitor
voltage (at the high‐side MOSFET gate)
A series resistor, 1Ω to 4Ω, may be added to customize the
rise time of the high‐side output. Slowing down this output
allows setting the phase node rising slew rate and limits
the surge current into the boot capacitor on start‐up.
SUPPLY DECOUPLING CAPACITOR
VCC decoupling to the IR3598 is provided by a 0.1uF
bypass capacitor C_Vcc located close to the supply input pin.
A series resistor Rvcc, typically 10Ω, is added in series with
the supply voltage to filter high frequency ringing and
noise. A 1.0uF or higher capacitor is recommended for the
VDRV decoupling capacitor, CDRV.
PCB LAYOUT CONSIDERATIONS
PCB layout and design is important to driver performance
in voltage regulator circuits due to the high current slew
rate (di/dt) during MOSFET switching.
 Locate all power components in each phase as
close to each other as practically possible in order
to minimize parasitics and losses, allowing for
reasonable airflow.
 Input supply decoupling and bootstrap capacitors
should be physically located close to their
respective IC pins.
 High current paths like the gate driver traces
should be as wide and short as practically possible.
 Trace inductances to the high‐ and low‐side
MOSFETs should be minimized.
 The ground connection of the IC should be as close
as possible to the low‐side MOSFET source.
 Use of a copper plane under and around the IC
and thermal vias to connect to buried copper
layers improves the thermal performance.
MOSFET stages should be well bypassed with capacitors
placed between the drain of the HIGH‐side MOSFET and
the source of the LOW‐side MOSFET.
13 December 6, 2011 | FINAL | V1.05