X9408 Datasheet, PDF (9/21 Pages) Intersil Corporation – Low Noise/Low Power/2-Wire Bus

X9408
DETAILED OPERATION
All XDCP potentiometers share the serial interface
and share a common architecture. Each potentiometer
has a Wiper Counter Register and four Data
Registers. A detailed discussion of the register
organization and array operation follows.
Wiper Counter Register
The X9408 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The Wiper Counter
Register can be envisioned as a 6-bit parallel and
serial load counter with its outputs decoded to select
one of sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/ Decrement
instruction. Finally, it is loaded with the contents of its
data register zero (DR0) upon power-up.
The WCR is a volatile register; that is, its contents are
lost when the X9408 is powered-down. Although the
register is automatically loaded with the value in R0
upon power-up, it should be noted this may be
different from the value present at power-down.
Data Registers
Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the WCR. It should be noted
all operations changing data in one of these registers
is a nonvolatile operation and will take a maximum of
10ms.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
Register Descriptions
Data Registers, (6-Bit), Nonvolatile
D5
D4
D3
D2
D1
NV
NV
NV
NV
NV
(MSB)
D0
NV
(LSB)
Four 6-bit Data Registers for each XDCP. (sixteen 6-
bit registers in total).
– {D5~D0}: These bits are for general purpose not vol-
atile data storage or for storage of up to four differ-
ent wiper values. The contents of Data Register 0
are automatically moved to the wiper counter regis-
ter on power-up.
Wiper Counter Register, (6-Bit), Volatile
WP5 WP4 WP3 WP2 WP1
V
V
V
V
V
(MSB)
WP0
V
(LSB)
One 6-bit Wiper Counter Register for each XDCP.
(Four 6-bit registers in total.)
– {D5~D0}: These bits specify the wiper position of the
respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register 0.
The contents of the WCR can be loaded from any of
the other Data Register or directly. The contents of
the WCR can be saved in a DR.
9
FN8191.2
September 19, 2005