X9408 Datasheet, PDF (14/21 Pages) Intersil Corporation – Low Noise/Low Power/2-Wire Bus

X9408
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing level
V_CC x 0.1 to V_CC x 0.9
10ns
V_CC x 0.5
EQUIVALENT A.C. LOAD CIRCUIT
SDA Output
5V
1533Ω
100pF
Circuit #3 SPICE Macro Model
V_H/R_H
R_TOTAL
C_H
C_W
V_L/R_L
C_L
10pF
10pF
25pF
V_W/R_W
AC TIMING (over recommended operating condition)
Symbol
f_SCL
t_CYC
t_HIGH
t_LOW
t_SU:STA
t_HD:STA
t_SU:STO
t_SU:DAT
t_HD:DAT
t_R
t_F
t_AA
t_DH
T_I
t_BUF
t_SU:WPA
t_HD:WPA
Parameter
Clock frequency
Clock cycle time
Clock high time
Clock low time
Start setup time
Start hold time
Stop setup time
SDA data input setup time
SDA data input hold time
SCL and SDA rise time
SCL and SDA fall time
SCL low to SDA data output valid time
SDA Data output hold time
Noise suppression time constant at SCL and SDA inputs
Bus free time (prior to any transmission)
WP, A0, A1, A2 and A3 setup time
WP, A0, A1, A2 and A3 hold time
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
t_WR
Parameter
High-voltage write cycle time (store instructions)
Min.
2500
600
1300
600
600
600
100
30
50
50
1300
0
0
Max.
400
300
300
900
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Typ.
5
Max.
10
Unit
ms
14
FN8191.2
September 19, 2005