ISLA224S_14 Datasheet, PDF (9/38 Pages) Intersil Corporation – Dual 14-Bit, 250/200/125 MSPS JESD204B High Speed Serial Output ADC

ISLA224S
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
MIN
MAX
SYMBOL
CONDITION
(Note 6)
TYP
(Note 6) UNITS
LVDS Inputs
SYNCP, SYNCN Setup Time (with Respect to the Positive Edge of
t_RSTS AVDD,
400
75
ps
CLKP)
OVDD = 1.7V to
1.9V, T_A = -40°C
to +85°C
SYNCP, SYNCN Hold Time (with respect to the positive edge of
CLKP)
CML Outputs
t_RSTH
AVDD,
OVDD = 1.7V to
1.9V, T_A = -40°C
to +85°C
150
350
ps
Output Rise Time
Output Fall Time
Data Output Duty Cycle
t_R
165
ps
t_F
145
ps
50
%
Differential Output Resistance
100
Ω
Differential Output Voltage (Note 13)
760
mV_P-P
SPI INTERFACE (Notes 14, 15)
SCLK Period
t
CLK
Write Operation
7
cycles
t_CLK
Read Operation
16
cycles
CSB↓ to SCLK↑ Setup Time
t_S
Read or Write
2
cycles
CSB↑ after SCLK↑ Hold Time
t_H
Read or Write
5
cycles
Data Valid to SCLK↑ Setup Time
t_DS
Read or Write
6
cycles
Data Valid after SCLK↑ Hold Time
t_DH
Read or Write
4
cycles
Data Valid after SCLK↓ Time
t_DVR
Read
4
cycles
NOTES:
11. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
12. The synchronous clock divider reset function is available as a (SPI-programmable) overload on the SYNC input.
13. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak single-ended swing is 1/2 of the differential swing.
14. The SPI interface timing is directly proportional to the ADC sample period (t_S). Values above reflect multiples of a 4ns sample period, and must be
scaled proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
15. The SPI may operate asynchronously with respect to the ADC sample clock.
9
FN7911.2
April 25, 2013