ISL76322 Datasheet, PDF (9/13 Pages) Intersil Corporation – 16-Bit Long-Reach Video Automotive Grade SERDES

Timing Diagrams
BIT BOUNDARY
TXP
VCM
ISL76322
BIT BOUNDARY
BIT BOUNDARY
Tx SETTING
0x0F
0x00
0xFF
0xF0
TXN
PCLK_IN
(RISING EDGE
DEFAULT)
RGBA[7:0],
RGBC[7:0]
VOD TRANSITION BIT
VOD NON-TRANSITION BIT
FIGURE 2. VOD vs TX SETTING
SERIALIZER MODE
1/FIN
tIDC
tIS
tIH
VALID DATA
VALID DATA DATA IGNORED DATA IGNORED VALID DATA
tIS
tIH
HSYNC OR VSYNC
(HVSYNCPOL = ‘0’)
DATAEN
(ACTIVE ‘1’ DEFAULT)
FIGURE 3. PARALLEL VIDEO INPUT TIMING
PCLK_OUT
(RISING EDGE
DEFAULT)
RGBA[7:0],
RGBC[7:0]
1/FOUT
DESERIALIZER MODE
tOR
t_OF
tDV
VALID DATA
VALID DATA
tDV
PREVIOUS DATA HELD
t_ODC
VALID DATA
HSYNC OR VSYNC
( HVSYNCPOL = ‘0’)
DATAEN
(ACTIVE ‘1’ DEFAULT)
FIGURE 4. PARALLEL VIDEO OUTPUT TIMING
9
January 31, 2011
FN7611.0