ISL6614B_06 Datasheet, PDF (9/11 Pages) Intersil Corporation – Dual Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP

ISL6614B
suggestions. When designing the driver into an application, it
is recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses due to
the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated with EQs. 2 and 3, respectively,
P_{Qg_TOT} = 2 • P_{Qg_Q1} + 2 • P_{Qg_Q2} + I_Q • VCC
P _{Q g _Q1}
=
Q_{-----G-----1----}•_-----P_----V_-----C_----C_-----²_-
V_GS1
•
F_SW
•
N_Q
1
P _{Q g _Q2}
=
Q_{-----G-----2----}•_-----P_----V_----C_-----C_-----²_-
V_GS2
•
F_SW
•
N_Q2
(EQ. 2)
I_DR
=



Q_{-----G-----1----}•_-----N_----Q-----1-
V_GS1
+
-^Q----^G---_V--²--_G--^•---_S--^N-₂---^Q-----²-_{}
• F_SW • 2 + I_Q
(EQ. 3)
where the gate charge (Q_G1 and Q_G2) is defined at a
particular gate to source voltage (V_GS1and V_GS2) in the
corresponding MOSFET datasheet; I_Q is the driver’s total
quiescent current with no load at both drive outputs; N_Q1
and N_Q2 are number of upper and lower MOSFETs,
respectively; PVCC is the drive voltages for both upper and
lower FETs, respectively. The I_Q*VCC product is the
quiescent power of the driver without capacitive load and is
typically 200mW at 300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R_G1 and R_G2) and the internal gate resistors
(R_GI1 and R_GI2) of MOSFETs. Figures 3 and 4 show the
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as:
P_DR = 2 • P_{DR_UP} + 2 • P_{DR_LOW} + I_Q • VCC
(EQ. 4)
P _{D R _UP}
=



-_R----_H----_I--₁--^R---+--^H--_R--^I--¹-_E----_X----_T---₁--
+
R^-----_L^---_O^-----₁^{R----+-L---O-}R^----1-_E^----_X^----_T^---₁^- _{}
•
P_{-----Q----g----_--Q-----1-}
2
P _{D R _LOW}
=



-_R----_H----_I--₂--^R---+--^H--_R--^I--²-_E----_X----_T---₂--
+
R^-----_L^---_O^-----₂^{R----+-L---O-}R^----2-_E^----_X^----_T^---₂^- _{}
• ^P-----^Q----^g----^_--^Q-----²-
2
R_EXT1
=
R_G
1
+
R_{-----G-----I-1--}
N_Q1
R_EXT2
=
R_G2
+
R_{-----G-----I-2--}
N_Q2
PVCC
BOOT
R_HI1
R_LO1
PHASE
C_GD
G
R_G1
R_GI1
C_GS
S
D
C_DS
Q1
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
R_HI2
R_LO2
C_GD
G
R_G2
R_GI2
C_GS
S
D
C_DS
Q2
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Layout Considerations
For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.
Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
DRAINs of lower FETs and the power ground. Thus, smaller
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
in between the power components is required for good
airflow. The traces from the drivers to the FETs should be
kept short and wide to reduce the inductance of the traces
and to promote clean drive signals.
9
FN9206.2
January 3, 2006