ISL6611A_13 Datasheet, PDF(9/14 Page) Intersil Corporation – Phase Doubler with Integrated Drivers and Phase Shedding Function

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ISL6611A_13 Datasheet, PDF (9/14 Pages) Intersil Corporation – Phase Doubler with Integrated Drivers and Phase Shedding Function

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Timing Diagram

ISL6611A

PWM

UGATE

LGATE

tPDLL

tPDHU

tPDLU

tRU

2.5V

tTSSHD

tRU

tPTS

tPDHL

tRL

tTSSHD

tFL

tFU

tPTS

FIGURE 1. TIMING DIAGRAM

Operation and Adaptive Shoot-Through Protection

Designed for high speed switching, the ISL6611A MOSFET

driver controls two-phase power trainsâ high-side and low-side

N-Channel FETs from one externally provided PWM signal.

A rising transition on PWM initiates the turn-off of the lower

MOSFET (see Figure 1). After a short propagation delay

[tPDLL], the lower gate begins to fall. Typical fall times [tFL]

are provided in the âElectrical Specificationsâ on page 8.

Adaptive shoot-through circuitry monitors the LGATE voltage

and turns on the upper gate following a short delay time

[tPDHU] after the LGATE voltage drops below ~1V. The

upper gate drive then begins to rise [tRU] and the upper

MOSFET turns on.

A falling transition on PWM indicates the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. The upper

gate begins to fall [tFU] after a propagation delay [tPDLU],

which is modulated by the current balance circuits. The

adaptive shoot-through circuitry monitors the UGATE-PHASE

voltage and turns on the lower MOSFET a short delay time,

tPDHL, after the upper MOSFETâs gate voltage drops below

1V. The lower gate then rises [tRL], turning on the lower

MOSFET. These methods prevent both the lower and upper

MOSFETs from conducting simultaneously (shoot-through),

while adapting the dead time to the gate charge

characteristics of the MOSFETs being used.

This driver is optimized for voltage regulators with large step

down ratio. The lower MOSFET is usually sized larger

compared to the upper MOSFET because the lower

MOSFET conducts for a longer time during a switching

period. The lower gate driver is therefore sized much larger

to meet this application requirement. The 0.4Î©

ON-resistance and 4A sink current capability enable the

lower gate driver to absorb the current injected into the lower

gate through the drain-to-gate capacitor (CGD) of the lower

MOSFET and help prevent shoot through caused by the self

turn-on of the lower MOSFET due to high dV/dt of the

switching node.

Tri-State PWM Input

A unique feature of the ISL6611A is the adaptable tri-state

PWM input. Once the PWM signal enters the shutdown

window, either MOSFET previously conducting is turned off.

If the PWM signal remains within the shutdown window for

longer than 25ns of the previously conducting MOSFET, the

output drivers are disabled and both MOSFET gates are

pulled and held low. The shutdown state is removed when

the PWM signal moves outside the shutdown window. The

PWM Tri-state rising and falling thresholds outlined in the

âElectrical Specificationsâ on page 8 determine when the

lower and upper gates are enabled. During normal operation

in a typical application, the PWM rise and fall times through

the shutdown window should not exceed either outputâs

turn-off propagation delay plus the MOSFET gate discharge

time to ~1V. Abnormally long PWM signal transition times

through the shutdown window will simply introduce

additional dead time between turn off and turn on of the

synchronous bridgeâs MOSFETs. For optimal performance,

no more than 100pF parasitic capacitive load should be

present on the PWM line of ISL6611A (assuming an Intersil

PWM controller is used).

Bootstrap Considerations

This driver features an internal bootstrap diode. Simply

adding an external capacitor across the BOOT and PHASE

FN6881.1

August 28, 2012

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