ISL6611A_13 Datasheet, PDF(12/14 Page) Intersil Corporation – Phase Doubler with Integrated Drivers and Phase Shedding Function

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ISL6611A_13 Datasheet, PDF (12/14 Pages) Intersil Corporation – Phase Doubler with Integrated Drivers and Phase Shedding Function

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ISL6611A

< 400ns. For a good current balance, it is recommended to

keep at least 200ns sampling time, if not the full 400ns.

Equations 5 and 6 show the maximum frequency of each

channel in interleaving mode and synchronous mode,

respectively. Assume 80ns each for tPD, tLR, tLF and 200ns

each for tAVSAMP, tBLANK, the maximum channel frequency

can be set to no more than 500kHz at interleaving mode and

1MHz at synchronous mode, respectively, for an application

with a maximum duty cycle of 20%. The maximum duty cycle

occurs at the maximum output voltage (overvoltage trip level

as needed) and at the minimum input voltage (undervoltage

trip level as needed). The efficiency of the voltage regulator

is also a factor in the theoretical approximation. Figure 7

shows the relationship between the maximum channel

frequency and the maximum duty cycle in the previous

assumed conditions.

For interleaving mode (SYNC = â0â),

FSW(MAX) â -(--t--A----V----S----A---M-----P-----+-----t-1-P----âD-----2+-----ât--L-D---R-(---M-+----A-t--L--X-F---)--+-----t--B----L---A----N----K----)---â---2--

D(MAX) â -VV----OI---N--U--(---MT----(-I-M-N-----A)----âX---Î·--)

(EQ. 5)

For synchronous mode (SYNC = â1â),

FSW(MAX) â (---t--A----V----S----A---M-----P-----+-----t-1-P----âD-----D+-----(t--ML----R-A----+-X----t)--L---F-----+-----t--B----L---A----N----K----)

(EQ. 6)

SYNCHRONOUS

INTERLEAVING

0.1

100

DUTY CYCLE (%)

FIGURE 7. MAXIMUM CHANNEL SWITCHING FREQUENCY

vs MAXIMUM DUTY CYCLE IN ASSUMED

CONDITIONS

Note that the PWM controller should be set to 2 x FSW for

interleaving mode and the same switching frequency for the

synchronous mode.

Application Information

MOSFET and Driver Selection

The parasitic inductances of the PCB and of the power

devicesâ packaging (both upper and lower MOSFETs) can

cause serious ringing, exceeding absolute maximum rating

of the devices. The negative ringing at the edges of the

PHASE node could increase the bootstrap capacitor voltage

through the internal bootstrap diode, and in some cases, it

may overstress the upper MOSFET driver. Careful layout,

proper selection of MOSFETs and packaging, as well as the

proper driver can go a long way toward minimizing such

unwanted stress.

PVCC

BOOT

RHI1

RLO1

UGATE

PHASE RPH = 1Î© TO 2Î©

FIGURE 8. PHASE RESISTOR TO MINIMIZE SERIOUS

NEGATIVE PHASE SPIKE IF NEEDED

The selection of D2-PAK, or D-PAK packaged MOSFETs, is

a much better match (for the reasons discussed) for the

ISL6611A with a phase resistor (RPH), as shown in Figure 8.

Low-profile MOSFETs, such as Direct FETs and multi-source

leads devices (SO-8, LFPAK, PowerPAK), have low parasitic

lead inductances and can be driven by ISL6611A (assuming

proper layout design) without the phase resistor (RPH).

Layout Considerations

A good layout helps reduce the ringing on the switching

node (PHASE) and significantly lower the stress applied to

the output drives. The following advice is meant to lead to an

optimized layout and performance:

â¢ Keep decoupling loops (VCC-GND, PVCC-PGND and

BOOT-PHASE) short and wide, at least 25 mils. Avoid

using vias on decoupling components other than their

ground terminals, which should be on a copper plane with

at least two vias.

â¢ Minimize trace inductance, especially on low-impedance

lines. All power traces (UGATE, PHASE, LGATE, PGND,

PVCC, VCC, GND) should be short and wide, at least

25 mils. Try to place power traces on a single layer,

otherwise, two vias on interconnection are preferred

where possible. For no connection (NC) pins on the QFN

FN6881.1

August 28, 2012

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