ISL6594D_14 Datasheet, PDF (9/11 Pages) Intersil Corporation – Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features

ISL6594D
vias. This combination of vias for vertical heat escape,
extended copper plane, and buried planes for heat
spreading allows the IC to achieve its full thermal potential.
Upper MOSFET Self Turn-On Effects at Start-up
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, because of
self-coupling via the internal C_GD of the MOSFET, the
UGATE could momentarily rise up to a level greater than the
threshold voltage of the MOSFET. This could potentially turn
on the upper switch and result in damaging inrush energy.
Therefore, if such a situation (when input bus powered up
before the bias of the controller and driver is ready) could
conceivably be encountered, it is a common practice to
place a resistor (R_UGPH) across the gate and source of the
upper MOSFET to suppress the Miller coupling effect. The
value of the resistor depends mainly on the input voltage’s
rate of rise, the C_GD/C_GS ratio, as well as the gate-source
threshold of the upper MOSFET. A higher dV/dt, a lower
C_DS/C_GS ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, a
5kΩ to 10kΩ resistor is typically sufficient, not affecting
normal performance and efficiency.
The coupling effect can be roughly estimated using
Equation 5, which assume a fixed linear input ramp and
neglect the clamping effect of the body diode of the upper
drive and the bootstrap capacitor. Other parasitic
components such as lead inductances and PCB
capacitances are also not taken into account. These
equations are provided for guidance purpose only.
Therefore, the actual coupling effect should be examined
using a very high impedance (10MΩ or greater) probe to
ensure a safe design margin.
⎛
---------–----^V----^D-----^S-----------⎞
V _{G S _MILLER}
=
d_----V_---
dt
⋅
R
⋅
C_rs
⎜
⎜
s⎜
1
–
e
d_----V_---
dt
⋅
R
⋅
Ci
⎟
s s⎟
⎟
⎜
⎟
⎝
⎠
(EQ. 5)
R = R_UGPH + R_GI
C_rss = C_GD
C_iss = C_GD + C_GS
PVCC
DU
DL
BOOT
C_BOOT
UGATE G
PHASE
C_GD
VIN
D
C_DS
R_GI
C_GS
S
Q_UPPER
FIGURE 5. GATE TO SOURCE RESISTOR TO REDUCE
UPPER MOSFET MILLER COUPLING
9
FN9282.1
December 3, 2007