ISL6594D_14 Datasheet, PDF (8/11 Pages) Intersil Corporation – Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features

ISL6594D
improvement suggestions. When designing the driver into an
application, it is recommended that the following calculations
are used to ensure safe operation at the desired frequency for
the selected MOSFETs. The total gate drive power losses due
to the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated with Equations 2 and 3, respectively:
P_{Qg_TOT} = P_{Qg_Q1} + P_{Qg_Q2} + I_Q • VCC
P _{Q g _Q1}
=
Q_{-----G-----1----}•_-----P_----V_----C_-----C_-----²_-
V_GS1
•
f_SW
•
N_Q1
P _{Q g _Q2}
=
Q_{-----G-----2----}•_-----P_----V_-----C_----C_-----²_-
V_GS2
•
f_S
W
•
N_Q
2
(EQ. 2)
I_DR
=
⎛
⎜
⎝
Q_{-----G-----1----}•_-----P_----V_-----C_----C_------•_----N_{-----Q----1--}
V_GS1
+
Q_{-----G-----2----}•_-----P_-V---V_-G---C_-S----C_2------•_----N_{-----Q----2--⎠⎟⎞}
• f_SW + I_Q
(EQ. 3)
where the gate charge (Q_G1 and Q_G2) is defined at a
particular gate to source voltage (V_GS1and V_GS2) in the
corresponding MOSFET datasheet; I_Q is the driver’s total
quiescent current with no load at both drive outputs; N_Q1
and N_Q2 are number of upper and lower MOSFETs,
respectively; PVCC is the drive voltage for both upper and
lower FETs. The I_Q*VCC product is the quiescent power of
the driver without capacitive load and is typically 116mW at
300kHz and VCC = PVCC = 12V.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R_G1 and R_G2) and the internal gate resistors
(R_GI1 and R_GI2) of MOSFETs. Figures 3 and 4 show the
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as:
P_DR = P_{DR_UP} + P_{DR_LOW} + I_Q • VCC
(EQ. 4)
P _{D R _UP}
=
⎛
⎜
⎝
-------------^R-----^H----^I--¹--------------
R_HI1 + R_EXT1
+
R^-----_L^---_O^-----₁^{R----+-L---O-}R^----1-_E^----_X^----_T^---₁^- _{⎠⎟⎞}
•
P_{-----Q----g----_--Q-----1-}
2
P _{D R _LOW}
=
⎛
⎜
⎝
-------------^R-----^H----^I--²--------------
R_HI2 + R_EXT2
+
R^-----_L^---_O^-----₂^{R----+-L---O-}R^----2-_E^----_X^----_T^---₂^- _{⎠⎟⎞}
•
P_{-----Q----g----_--Q-----2-}
2
R_EXT1
=
R_G
1
+
R_{-----G-----I-1--}
N_Q1
R_EXT2
=
R_G2
+
R_{-----G-----I-2--}
N_Q2
PVCC
BOOT
R_HI1
R_LO1
PHASE
C_GD
G
R_G1
R_GI1
C_GS
S
D
C_DS
Q1
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
R_HI2
R_LO2
C_GD
G
R_G2
R_GI2
C_GS
S
D
C_DS
Q2
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Application Information
Layout Considerations
The parasitic inductances of the PCB and of the power
devices’ packaging (both upper and lower MOSFETs) can
cause serious ringing, exceeding absolute maximum rating
of the devices. Careful layout can help minimize such
unwanted stress. The following advice is meant to lead to an
optimized layout:
• Keep decoupling loops (PVCC-GND and BOOT-PHASE)
as short as possible.
• Minimize trace inductance, especially on low-impedance
lines. All power traces (UGATE, PHASE, LGATE, GND,
PVCC) should be short and wide, as much as possible.
• Minimize the inductance of the PHASE node. Ideally, the
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
• Minimize the current loop of the output and input power
trains. Short the source connection of the lower MOSFET
to ground as close to the transistor pin as feasible. Input
capacitors (especially ceramic decoupling) should be
placed as close to the drain of upper and source of lower
MOSFETs as possible.
In addition, for heat spreading, place copper underneath the
IC whether it has an exposed pad or not. The copper area
can be extended beyond the bottom area of the IC and/or
connected to buried power ground plane(s) with thermal
8
FN9282.1
December 3, 2007