ISL6422 Datasheet, PDF (9/19 Pages) Intersil Corporation – Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs

ISL6422
Functional Pin Descriptions
SYMBOL
SDA
SCL
VSW1 and VSW2
PGND1 and PGND2
CS1 and CS2
SGND
TCAP1 and TCAP2
BYP
TXT1 and TXT2
VCC
GATE1 and GATE2
VOUT1 and VOUT2
ADDR0 and ADDR1
Bidirectional data from/to I²C bus.
Clock from I²C bus.
FUNCTION
Input of the linear post-regulator.
Dedicated ground for the output gate driver of respective PWM.
Current sense input; connect the sense resistor Rsc at this pin for desired overcurrent value for respective PWM.
Small signal ground for the IC.
Capacitor for setting rise and fall time of the output of LNB A and LNB B respectively. Typical value is 0.22µF.
Bypass capacitor for internal 5V.
TXT1 and TXT2 are the Tone Transmit signal inputs used to change the tone decoder threshold. The threshold is 200mV
max for the Rx mode when the TXT1 and TXT2 are set low. The threshold is 400mV min in the Tx mode when TXT1
and TXT2 are set high. If Tx/Rx mode is set by I²C bit TTH(1 ,2), when TTH(1, 2) = 1, then TXT(1, 2) will be driven high
(5V) by an on-chip driver.
Main power supply to the chip.
These are the device outputs of PWM A and PWM B respectively. These high current driver outputs are capable of
driving the gate of a power FET. These outputs are actively held low when V_CC is below the UVLO threshold.
Output voltage for LNB A and LNB B respectively.
Address pins select four different device addresses per Table 19.
EXTM1 and EXTM2
FLT
These pins can be used in two ways:
1. As an input for externally modulated Diseqc tone signal that is transferred symmetrically onto V_OUT.
2. Alternatively apply a Diseqc modulation envelope that modulates an internal tone and then transfers it symmetrically
onto V_OUT.
This is an open drain output from the controller. When the FLT goes low, it indicates that an Over Temperature has
occurred. The processor should then look at the I²C register to get the actual cause of the error. A high on the FLT
indicates that the device is functioning normally.
CPVOUT, CPSWIN,
CPSWOUT
A 47nF charge pump cap is connected to CPVOUT. Connect a 1.5nF capacitor between CPSWIN and CPSWOUT.
SELVTOP1 and
SELVTOP2
The following description applies to both pins and both bits.
When
When
this
this
pin
pin
is
is
low, the V_OUT is in the 13V/14V range
high, the 18V/19V range is selected by
selected by the I²C bit VBOT1 and
the I²C bit VTOP1 and VTOP2.
VBOT2.
The voltage select pin voltage VSPEN1 and VSPEN2 I²C bit must be set low for the SELVTOP1 and SELVTOP2 pins
to be active. Setting VSPEN1 and VSPEN2 high disables these pins and voltage selection will be done using the I²C
bits VBOT1 and VBOT2 and VTOP1 and VTOP2 only.
TDIN1 and TDIN2
TDIN1 and TDIN2 are the tone decoder inputs for channels 1 and 2.
TDOUT1 and TDOUT2 TDOUT1 and TDOUT2 are the tone detector outputs for channels 1 and 2. TDOUT1 and TDOUT2 are open drain
outputs.
AGND
Analog ground for the IC.
9
FN9190.1
April 10, 2007