ISL6422 Datasheet, PDF (16/19 Pages) Intersil Corporation – Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs

ISL6422
TABLE 18. CONTROL REGISTER SR8 CONFIGURATION
SR8H SR8M SR8L EN2
X
X VTOP2 VBOT2
FUNCTION
1
1
1
1
X
X
0
0 SR4 is selected
1
1
1
1
X
X
0
0 VSPEN2 = SELVTOP2 = 0, V_OUT1 = 13V,
V_BOOST1 = 13V + V_DROP
1
1
1
1
X
X
0
1 VSPEN2 = SELVTOP2 = 0, V_OUT1 = 14V,
V_BOOST1 = 14V + V_DROP
1
1
1
1
X
X
1
0 VSPEN2 = SELVTOP2 = 0, V_OUT1 = 13V,
V_BOOST1 = 13V + V_DROP
1
1
1
1
X
X
1
1 VSPEN2 = SELVTOP2 = 0, V_OUT1 = 14V,
V_BOOST1 = 14V + V_DROP
1
1
1
1
X
X
0
0 VSPEN2 = 0,SELVTOP2 = 1, V_OUT1 = 18V,
V_BOOST1 = 18V + V_DROP
1
1
1
1
X
X
0
1 VSPEN2 = 0, SELVTOP2 = 1, V_OUT1 = 18V,
V_BOOST1 = 18V + V_DROP
1
1
1
1
X
X
1
0 VSPEN2 = 0, SELVTOP2 = 1, V_OUT1 = 19V,
V_BOOST1 = 19V + V_DROP
1
1
1
1
X
X
1
1 VSPEN2 = 0, SELVTOP2 = 1, V_OUT1 = 19V,
V_BOOST1 = 19V + V_DROP
1
1
1
1
X
X
0
0 VSPEN2 = 1, SELVTOP2 = X, V_OUT1 = 13V,
V_BOOST1 = 13V + V_DROP
1
1
1
1
X
X
0
1 VSPEN2 = 1, SELVTOP2 = X, V_OUT1 = 14V,
V_BOOST1 = 14V + V_DROP
1
1
1
1
X
X
1
0 VSPEN2 = 1, SELVTOP2 = X, V_OUT1 = 18V,
V_BOOST1 = 18V + V_DROP
1
1
1
1
X
X
1
1 VSPEN2 = 1, SELVTOP2 = X, V_OUT1 = 19V,
V_BOOST1 = 19V + V_DROP
1
1
1
0
X
X
X
X PWM and Linear for channel 1 disabled
NOTE: X is a “Don’t Care” for the Write mode.
Received Data (I²C bus READ MODE)
The ISL6422 can provide to the master a copy of the system
register information via the I²C bus in read mode. The read
mode is master-activated by sending the chip address with
the R/W bit set to 1. At the following master-generated clock
bits, the ISL6422 issues a byte on the SDA data bus line
(MSB transmitted first).
At the ninth clock bit, the MCU master can:
• Acknowledge the reception, thus starting the transmission
of another byte from the ISL6422.
• Not acknowledge, thus stopping the read mode
communication.
While the whole register is read back by the microprocessor,
the following read-only bits convey diagnostic information
about the ISL6422.
• OUC1 and OUC2 (Over or Undercurrent bits)
• UV1 and UV2 (Over or Undervoltage bits)
• TPR1 and TPR2 (Tone present bits)
• OTF (Over-temperature fault bit).
Power–On I²C Interface Reset
The I²C interface built into the ISL6422 is automatically reset
at power-on. The I²C interface block will receive a Power OK
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I²C commands and the
system register SR1 and SR2 are initialized to all zeros, thus
keeping the power blocks disabled. Once the V_CC rises
above UVLO, the POWER OK signal given to the I²C
interface block will be HIGH, the I²C interface becomes
operative and the SRs can be configured by the main
microprocessor. About 400mV of hysteresis is provided in
the UVLO threshold to avoid false triggering of the power-on
reset circuit. (I²C comes up with EN = 0; EN goes HIGH at
the same time as (or later than) all other I²C data for that
PWM becomes valid).
16
FN9190.1
April 10, 2007