ISL6224 Datasheet, PDF (9/13 Pages) Intersil Corporation – Single Output Mobile-Friendly PWM Controller

ISL6224
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load
circuitry for specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications, at 300kHz, for the bulk
capacitors. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.
The stability requirement on the selection of the output
capacitor is that the ‘ESR zero’, f_Z, be between 1.2kHz and
30kHz. This range is set by an internal, single compensation
zero at 6kHz. The ESR zero can be a factor of five on either
side of the internal zero and still contribute to increased
phase margin of the control loop. Therefore:
C_OUT
=
---------------------¹----------------------
2 × π × ESR × f_Z
In conclusion, the output capacitors must meet three criteria:
1. They must have sufficient bulk capacitance to sustain the
output voltage during a load transient while the output
inductor current is slewing to the value of the load
transient
2. The ESR must be sufficiently low to meet the desired
output voltage ripple due to the output inductor current,
and
3. The ESR zero should be placed, in a rather large range,
to provide additional phase margin.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current and output capacitor(s) ESR. The ripple
voltage expression is given in the capacitor selection section
and the ripple current is approximated by the following
equation:
∆IL
=
V_{-----I--N-----}–_----V_{-----O----U----T--}
F_S × L
×
-^V----^O----^U----^T--
V_IN
where F_s is the switching frequency.
Input Capacitor Selection
The important parameters for the bulk input capacitor(s) are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage and 1.5 times is a conservative
guideline.
The AC RMS input current varies with load. Depending on
the specifics of the input power and it’s impedance, most (or
all) of this current is supplied by the input capacitor(s).
Use a mix of input bypass capacitors to control the voltage
ripple across the MOSFETs. Use ceramic capacitors for the
high frequency decoupling and bulk capacitors to supply the
RMS current. Small ceramic capacitors can be placed very
close to the upper MOSFET to suppress the voltage induced
in the parasitic circuit impedances.
For board designs that allow through-hole components, the
Sanyo OS-CON® series offer low ESR and good
temperature performance.
For surface mount designs, solid tantalum capacitors can be
used, but caution must be exercised with regard to the
capacitor surge current rating. These capacitors must be
capable of handling the surge-current at power-up. The TPS
series available from AVX is surge current tested.
MOSFET Considerations
The logic level MOSFETs are chosen for optimum efficiency
given the potentially wide input voltage range and output
power requirements. One dual N-Channel or two N-Channel
MOSFETs are used in each of the synchronous rectified
buck converters for the outputs. These MOSFETs should be
selected based upon r_DS(ON) , gate supply requirements,
and thermal management considerations.
The power dissipation includes two loss components;
conduction loss and switching loss. These losses are
distributed between the upper and lower MOSFETs
according to duty cycle (see the following equations). The
conduction losses are the main component of power
dissipation for the lower MOSFETs. Only the upper MOSFET
has significant switching losses, since the lower device turns
on and off into near-zero voltage.
P_UPPER
=
I_--O-----²_----×_-----r_{--D----S----(--O-----N----)---}×_-----V_{----O-----U----T-- + -}I_-O------×_-----V_{----I--N-----}×_-----t_{--S----W------}×_-----F_----S--
V_IN
2
P_LOWER
=
I_--O-----²_----×_-----r_{--D----S----(--O-----N----)---}×_-----(_---V_{----I--N-----}–_----V_{-----O----U----T----})
V_IN
The equations assume linear voltage-current transitions and
do not model power loss due to the reverse-recovery of the
lower MOSFET’s body diode.
The gate-charge losses are dissipated by the ISL6224 and
do not heat the MOSFETs. However, a large gate-charge
increases the switching time, t_SW which increases the upper
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications.
9
OS-CON® is a registered trademark of Sanyo Electric Company, LtdF.N(9Ja0p4a2n.7)
December 28, 2004