ISL6224 Datasheet, PDF (8/13 Pages) Intersil Corporation – Single Output Mobile-Friendly PWM Controller

ISL6224
Soft-Start Operation
Soft-start of the Synchronous Buck Converter is
accomplished by means of a capacitor connected from pin 7,
SOFT to ground. The soft-start time can be obtained from
the following equation:
Tss = -¹---^.--⁵---^V------^×-----^C----^s----^s-
5.0 µ A
Figure 4 shows the soft-start initiated by the ENABLE pin
being pulled high with the VIN input at 5.6V and the resulting
3.3V output and PGOOD signal. While the ENABLE pin is
held low, prior to t0, the output is off. When the EN pin is
pulled high, at t0, the voltage on the capacitor connected to
the soft-start pin rises linearly due to the internal 5µA current
source starts charging the capacitor. The output voltage
follows the voltage on the capacitor till it reaches the value of
0.9V at t1. At this moment, t1, the output voltage started
regulation. The soft-start is complete when PGOOD pin is
high at t2 and further rise of the voltage on the soft-start
capacitor does not affect the output voltage.
t0
t1
t2
FIGURE 4. MODE CONTROL WAVEFORMS
Power Good Status
The ISL6224 monitors the output voltage. A single power-
good signal, PGOOD, is issued when soft-start is completed
and the output is within 10% of it’s set point. After the soft-
start sequence is completed, undervoltage protection
latches the chip off when any of the monitored outputs drop
below 70% of its set point.
A ‘soft-crowbar’ function is implemented for an overvoltage
on the output. If the output voltage goes above 120% of its
nominal output level, the upper MOSFET is turned off and
the lower MOSFET is turned on. This ‘soft-crowbar’
condition will be maintained until the output voltage returns
to the regulation window and then normal operation will
continue.
This ‘soft-crowbar’ and monitoring of the output, prevents the
output voltage from ringing negative as the inductor current
flows in the ‘reverse’ direction through the lower MOSFET
and output capacitors.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors have unique requirements. In general,
the output capacitors should be selected to meet the
dynamic regulation requirements including ripple voltage
and load transients.
Selection of the output capacitors is also dependent on the
output inductor so some inductor analysis is required to
select the output capacitors.
One of the parameters limiting the converter’s response to a
load transient is the time required for the inductor current to
slew to its new level. Given a sufficiently fast control loop
design, the ISL6224 will provide either 0% or 94% duty cycle
in response to a load transient. The response time is the
time interval required to slew the inductor current from an
initial current value to the load current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitor(s). Minimizing the response time can minimize the
output capacitance required. If the load transient rise time is
slower than the inductor response time, as in a hard drive or
CD drive, this reduces the requirement on the output
capacitor.
The maximum capacitor value required to provide the full,
rising step, transient load current during the response time of
the inductor is:
C_OUT
=
--------^L----^O-----^×-----^I--^T----^R----^A----^N---------
(V_IN – V_OUT) × 2
×
--^I--^T----^R----^A----^N----
DV_OUT
Where: C_OUT is the output capacitor(s) required, L_O is the
output inductor, I_TRAN is the transient load current step, V_IN
is the input voltage, V_OUT is output voltage, and DV_OUT is
the drop in output voltage allowed during the load transient.
High frequency capacitors initially supply the transient
current and slow the load rate-of-change seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (equivalent series resistance) and
voltage rating requirements as well as actual capacitance
requirements. The output voltage ripple is due to the inductor
ripple current and the ESR of the output capacitors as
defined by:
V_RIPPLE = ∆IL × ESR
where, ∆IL is calculated in the Inductor Selection section.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
8
FN9042.7
December 28, 2004