ISL6208 Datasheet, PDF (9/11 Pages) Intersil Corporation – High Voltage Synchronous Rectified Buck MOSFET Driver

ISL6208
1000
Q_U =100nC
900 Q_L = 200nC
800
Q_U = 50nC
Q_L = 100nC
Q_U = 50nC
Q_L = 50nC
700
600
Q_U = 20nC
500
Q_L =50nC
400
300
200
100
0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
FREQUENCY (kHz)
FIGURE 9. POWER DISSIPATION vs FREQUENCY
where f_sw is the switching frequency of the PWM signal. V_U
and V_L represent the upper and lower gate rail voltage. Q_U
and Q_L is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The lV_CC V_CC product is the quiescent power
of the driver and is typically negligible.
Layout Considerations
Reducing Phase Ring
The parasitic inductances of the PCB and power devices
(both upper and lower FETs) could cause increased PHASE
ringing, which may lead to voltages that exceed the absolute
maximum rating of the devices. When PHASE rings below
ground, the negative voltage could add charge to the
bootstrap capacitor through the internal bootstrap diode.
Under worst-case conditions, the added charge could
overstress the BOOT and/or PHASE pins. To prevent this
from happening, the user should perform a careful layout
inspection to reduce trace inductances, and select low lead
inductance MOSFETs and drivers. D²PAK and DPAK
packaged MOSFETs have high parasitic lead inductances,
as opposed to SOIC-8. If higher inductance MOSFETs must
be used, a Schottky diode is recommended across the lower
MOSFET to clamp negative PHASE ring.
A good layout would help reduce the ringing on the phase
and gate nodes significantly:
• Avoid using vias for decoupling components where
possible, especially in the BOOT-to-PHASE path. Little or
no use of vias for VCC and GND is also recommended.
Decoupling loops should be short.
• All power traces (UGATE, PHASE, LGATE, GND, VCC)
should be short and wide, and avoid using vias. If vias
must be used, two or more vias per layer transition is
recommended.
• Keep the SOURCE of the upper FET as close as thermally
possible to the DRAIN of the lower FET.
• Keep the connection in between the SOURCE of lower
FET and power ground wide and short.
• Input capacitors should be placed as close to the DRAIN
of the upper FET and the SOURCE of the lower FET as
thermally possible.
Note: Refer to Intersil Tech Brief TB447 for more information.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal
pad of the QFN part to the power ground with multiple vias,
or placing a low noise copper plane underneath the SOIC
part is recommended. This heat spreading allows the part to
achieve its full thermal potential.
9
FN9115.3
August 7, 2008