ISL54062 Datasheet, PDF (9/16 Pages) Intersil Corporation – 1.8V to +6.5V, Sub-Ohm, Dual SPDT Analog Switch with Negative Signal Capability and Click and Pop Elimination

ISL54062
Test Circuits and Waveforms (Continued)
V_DC
0V
V_INx*
0V
t_D
t_D
*V_INx waveform for Click and Pop Elimination on NOx terminal.
For Click and Pop Elimination on NCx terminal invert V_INx.
t_D = 200ms measured at 50% points.
V_DC
V_DC
INx
220uF NCx
CLICK AND POP
CIRCUITRY
220uF
NOx
COMx
R_L
FIGURE 8A. CLICK AND POP WAVEFORM
FIGURE 8B. CLICK AND POP TEST CIRCUIT
FIGURE 8. CLICK AND POP ELIMINATION
Detailed Description
The ISL54062 is a bi-directional, dual single pole-double
throw (SPDT) analog switch that offers precise switching
from a single 1.8V to 6.5V supply with low ON-resistance
(0.83Ω), high speed operation (t_ON = 55ns, t_OFF = 18ns) and
negative signal swing capability. The device is especially
well suited for portable battery powered equipment due to its
low operating supply voltage (1.8V), low power consumption
(20nA @ 3V), and a tiny 1.8mmx1.4mm µTQFN package or a
3x3 TDFN package. The low ON-resistance and r_ON flatness
provide very low insertion loss and signal distortion for
applications that require signal switching with minimal
interference by the switch.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. The ISL54062
contains ESD protection diodes on each pin of the IC
(see Figure 9). These diodes connect to either a +Ring or
-Ring for ESD protection. To prevent forward biasing the
ESD diodes to the +Ring, V+ must be applied before any
input signals, and the input signal voltages must remain
between recommended operating range.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a logic pin or switch terminal goes
above the V+ rail.
Logic inputs can be protected by adding a 1kΩ resistor in
series with the logic input (see Figure 9). The resistor limits
the input current below the threshold that produces
permanent damage.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low r_ON switch. Alternatively, connecting
external Schottky diodes from the V+ rail to the signal pins
will shunt the fault current through the Schottky diode
instead of through the internal ESD diodes, thereby
protecting the switch. These Schottky diodes must be sized
to handle the expected fault current.
V+
+RING
V_COMx
CLAMP
V_NCx
V_NOx
1kΩ
LOGIC
INPUTS
GND
-RING
FIGURE 9. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL54062 construction is typical of most single supply
CMOS analog switches which have two supply pins: V+ and
GND. V+ and GND provide the CMOS switch bias and sets
their analog voltage limits. Unlike switches with a 5.5V
maximum supply voltage, the ISL54062’s 6.5V maximum
supply voltage provides plenty of head room for the 10%
tolerance of 5.5V supplies due to overshoot and noise
spikes.
9
FN6581.0
February 25, 2009