ISL3150E Datasheet, PDF (9/22 Pages) Intersil Corporation – ±16.5kV ESD, Large Output Swing, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers

ISL3150E, ISL3152E, ISL3153E, ISL3155E, ISL3156E, ISL3158E
Electrical Specifications
Test Conditions: V_CC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at V_CC = 5V,
T_A = +25°C (Note 6). Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP MIN
MAX
(°C) (Note 14) TYP (Note 14) UNITS
Receiver Skew | t_PLH - t_PHL |
t_SKD
(Figure 5)
Full
-
2.5
5
ns
Receiver Enable to Output
t_ZL
R_L = 1kΩ, C_L = 15pF, SW = V_CC
Full
-
Low
(Figure 6), (Note 10)
8
15
ns
Receiver Enable to Output
t_ZH
R_L = 1kΩ, C_L = 15pF, SW = GND
Full
-
High
(Figure 6), (Note 10)
7
15
ns
Receiver Disable from
Output Low
t_LZ
R_L = 1kΩ, C_L = 15pF, SW = V_CC
Full
-
(Figure 6)
8
15
ns
Receiver Disable from
Output High
t_HZ
R_L = 1kΩ, C_L = 15pF, SW = GND
Full
-
(Figure 6)
8
15
ns
Time to Shutdown
t_SHDN (Note 11)
Full
60
160
600
ns
Receiver Enable from
t_ZH(SHDN) R_L = 1kΩ, C_L = 15pF, SW = GND
Full
-
Shutdown to Output High
(Figure 6), (Notes 11, 13)
-
200
ns
Receiver Enable from
t_ZL(SHDN) R_L = 1kΩ, C_L = 15pF, SW = V_CC
Full
-
Shutdown to Output Low
(Figure 6), (Notes 11, 13)
-
200
ns
NOTES:
6. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground
unless otherwise specified.
7. Supply current specification is valid for loaded drivers when DE = 0V.
8. Applies to peak current. See “Typical Performance Curves” beginning on page 14 for more information.
9. Keep RE = 0 to prevent the device from entering SHDN.
10. The RE signal high time must be short enough (typically <100ns) to prevent the device from entering SHDN.
11. Transceivers are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 60ns, the parts
are guaranteed not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered
shutdown. See “Low Power Shutdown Mode” on page 13.
12. Keep RE = VCC, and set the DE signal low time >600ns to ensure that the device enters SHDN.
13. Set the RE signal high time >600ns to ensure that the device enters SHDN.
14. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
15. See Figure 8 for more information, and for performance over-temperature.
16. Tested according to TIA/EIA-485-A, Section 4.2.6 (±100V for 15µs at a 1% duty cycle).
17. Limits established by characterization and are not production tested.
Test Circuits and Waveforms
V_CC ^DE
DI
Z
D
Y
V_OD
R_L/2
R_L/2 VOC
V_CC ^DE
DI
Z
D
Y
V_OD
375Ω
V_CM
R_L = 60Ω
-7V TO +12V
375Ω
FIGURE 1A. V_OD AND V_OC
FIGURE 1B. V_OD WITH COMMON MODE LOAD
FIGURE 1. DC DRIVER TEST CIRCUITS
9
FN6363.2
July 30, 2009