ISL29018_14 Datasheet, PDF (9/19 Pages) Intersil Corporation – Digital Ambient Light Sensor and Proximity Sensor with Interrupt Function

ISL29018
I²C Interface
There are eight 8-bit registers available inside the ISL29018. The
two command registers define the operation of the device. The
command registers do not change until the registers are
overwritten. The two 8-bit data Read Only registers are for the ADC
output and the Timer output. The data registers contain the ADC's
latest digital output. The four 8-bit interrupt registers hold 16-bit
interrupt high and low thresholds.
The ISL29018’s I²C interface slave address is internally hard-wired
as 1000100. When 1000100x with x as R or W is sent after the
Start condition, this device compares the first seven bits of this byte
to its address and matches.
Figure 3 shows a sample one-byte read. Figure 4 shows a sample
one-byte write. The I²C bus master always drives the SCL (clock)
line, while either the master or the slave can drive the SDA (data)
line. Figure 4 shows a sample write. Every I²C transaction begins
with the master asserting a start condition (SDA falling while SCL
remains high). The following byte is driven by the master, and
includes the slave address and read/write bit. The receiving
device is responsible for pulling SDA low during the
acknowledgement period. Every I²C transaction ends with the
master asserting a stop condition (SDA rising while SCL remains
high).
For more information about the I²C standard, please consult the
Philips^™ I²C specification documents.
I²C DATA ^START
DEVICE ADDRESS W A REGISTER ADDRESS
STOP START DEVICE ADDRESS
A
DATA BYTE0
I²C SDA
IN
I²C SDA
OUT
A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A
SDA DRIVEN BY MASTER
A SDA DRIVEN BY MASTER A
A6 A5 A4 A3 A2 A1 A0 W A
SDA DRIVEN BY ISL29018
SDA DRIVEN BY MASTER
A D7 D6 D5 D4 D3 D2 D1 D0
I²C CLK
12 3456 789123456 789
123 45 67 89123456789
FIGURE 3. I²C READ TIMING DIAGRAM SAMPLE
I²C DATA
I²C SDA IN
I²C SDA OUT
I²C CLK IN
START
DEVICE ADDRESS
W A REGISTER ADDRESS
A
FUNCTIONS
A STOP
A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A B7 B6 B5 B4 B3 B2 B1 B0 A
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
1 234 5 67 8 9 1234 56 7 8 9 12 345 67 89
FIGURE 4. I²C WRITE TIMING DIAGRAM SAMPLE
9
FN6619.4
October 8, 2012