ISL23415_15 Datasheet, PDF (9/20 Pages) Intersil Corporation – Single, Low Voltage Digitally Controlled Potentiometer

Timing Diagrams (Continued)
Output Timing
CS
ISL23415
SCK
t_SO
SDO
SDI ^ADDR
MSB
t_V
XDCP™ Timing (for All Load Instructions)
CS
SCK
SDI
MSB
...
t_HO
...
...
...
t_DIS
LSB
LSB
t_DCP
V_W
SDO
Typical Performance Curves
0.4
0.30
*When CS is HIGH
SDO at Z or Hi-Z state
0.2
0.15
0
0
-0.2
-0.4
0
50
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 3. 10k DNL vs TAP POSITION, V_CC = 5V
-0.15
-0.30
0
50
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 4. 50k DNL vs TAP POSITION, V_CC = 5V
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9
FN7780.2
September 14, 2015