ICL7106_14 Datasheet, PDF (9/17 Pages) Intersil Corporation – 31/2 Digit, LCD/LED Display, A/D Converters

ICL7106, ICL7107, ICL7107S
a
a
a
a
fb
f bf b
gc
g
g
b
ec
ec ec
d
d
d
TYPICAL SEGMENT OUTPUT
V+
0.5mA
8mA
TO
SEGMENT
DIGITAL GROUND
7
SEGMENT
DECODE
7
SEGMENT
DECODE
7
SEGMENT
DECODE
LATCH
1000’s
100’s
10’s
1’s
COUNTER COUNTER COUNTER COUNTER
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
V+
CLOCK
†
4
LOGIC CONTROL
† THREE INVERTERS
ONE INVERTER SHOWN FOR CLARITY
40
39
38
OSC 1
OSC 2
OSC 3
1
37
500Ω
27
V+
TEST
DIGITAL
GROUND
FIGURE 8. ICL7107 DIGITAL SECTION
System Timing
Figure 9 shows the clocking arrangement used in the ICL7106
and ICL7107. Two basic clocking arrangements can be used:
1. Figure 9A. An external oscillator connected to pin 40.
2. Figure 9B. An R-C oscillator using all three pins.
The oscillator frequency is divided by four before it clocks the
decade counters. It is then further divided to form the three
convert-cycle phases. These are signal integrate (1000 counts),
reference deintegrate (0 to 2000 counts) and auto-zero (1000 to
3000 counts). For signals less than full scale, auto-zero gets the
unused portion of reference de-integrate. This makes a complete
measure cycle of 4,000 counts (16,000 clock pulses)
independent of input voltage. For three readings/second, an
oscillator frequency of 48kHz would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz,
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would be suitable. Note that 40kHz (2.5 readings/second) will
reject both 50Hz and 60Hz (also 400Hz and 440Hz).
INTERNAL TO PART
4
CLOCK
40
39
38
GND ICL7107
TEST ICL7106
FIGURE 9A.
INTERNAL TO PART
4
CLOCK
40
39
38
R
C
RC OSCILLATOR
FIGURE 9B.
FIGURE 9. CLOCK CIRCUITS
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9
FN3082.9
October 24, 2014