HIP6500_00 Datasheet, PDF (9/15 Pages) Intersil Corporation – Multiple Linear Power Controller with ACPI Control Interface

HIP6500
5VSB
S3
S5
12V
INTERNAL
VSEN2
DEVICE
DRV2
VSEN2
3V3SB
VCLK
FIGURE 8. 2.5/3.3V_MEM, 3.3V_SB AND VCLK TIMING DIAGRAM
Soft-Start Circuit
SOFT-START INTO SLEEP STATES (S3, S4/S5)
The 5VSB POR function initiates the soft-start sequence. An
internal 10µA current source charges an external capacitor.
The error amplifiers reference inputs are clamped to a level
proportional to the SS (soft-start) pin voltage. As the SS pin
voltage slews from about 1.25V to 2.5V, the input clamp
allows a rapid and controlled output voltage rise.
5VSB
(1V/DIV)
SOFT-START
(1V/DIV)
0V
V_OUT5 (5V_DUAL)
OUTPUT
VOLTAGES
(1V/DIV)
V_OUT1 (3.3V_SB)
0V
V_OUT3 (3.3V_DUAL)
V_OUT2
(2.5V_MEM)
V_OUT4
(2.5V_CLK)
T0 T1 T2
T3
T4
T5
TIME
FIGURE 9. SOFT-START INTERVAL IN A SLEEP STATE
(ALL OUTPUTS ENABLED)
Figure 9 shows the soft-start sequence for the typical
application start-up in sleep state with all output voltages
enabled. At time T0 5VSB (bias) is applied to the circuit. At
time T1 the 5VSB surpasses POR level. An internal fast
charge circuit quickly raises the SS capacitor voltage to
approximately 1V, then the 10µA current source continues
the charging. The soft-start capacitor voltage reaches
approximately 1.25V at time T2, at which point the 3.3V_SB
error amplifiers’ reference input starts its transition, causing
the output voltage to ramp up proportionally. The ramp-up
continues until time T3 when the 3.3V_SB voltage reaches the
set value. After the 3.3V_SB reached its set value, as the soft-
start capacitor voltage reaches approximately 2.75V, the
under-voltage monitoring circuit of this output is activated
and the soft-start capacitor is quickly discharged to
approximately 1.25V. Following the 3ms (typical) time-out
between T3 and T4, the memory and enabling pins’
selection are latched in, and the soft-start capacitor
commences a second ramp-up designed to smoothly bring
up the remainder of the voltages required by the system. At
time T5 all voltages are within regulation limits, and as the
SS voltage reaches 2.75V, all the UV monitors are activated
and the SS capacitor is quickly discharged to 1.25V, where it
remains until the next transition.
+5VSB
+12V_IN
INPUT VOLTAGES
(2V/DIV)
+5V_IN
+3.3V_IN
0V
OUTPUT
VOLTAGES
(1V/DIV)
V_OUT1 (3.3V_SB)
DLA PIN
(2V/DIV)
SOFT-START
(1V/DIV)
V_OUT5 (5V_DUAL)
V_OUT3 (3.3V_DUAL)
V_{OUT2, 4}
(2.5V_MEM, 2.5V_CLK)
0V
T0 T1
T2
T3
TIME
FIGURE 10. SOFT-START INTERVAL IN ACTIVE STATE
(2.5/3.3V_MEM OUTPUT SHOWN IN 2.5V SETTING)
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