HIP6500_00 Datasheet, PDF (13/15 Pages) Intersil Corporation – Multiple Linear Power Controller with ACPI Control Interface

HIP6500
the supplied outputs. At the transition between active and
sleep states, this phenomena could result in the 5VSB
voltage dropping below the POR level (typically 4.1V) and
temporarily disabling the HIP6500. The solution to a
potential problem such as this is using larger input
capacitors with a lower total combined ESR.
Transistor Selection/Considerations
The HIP6500 usually requires one P-Channel (or bipolar
PNP), two N-Channel MOSFETs and two bipolar NPN
transistors.
One important criteria for selection of transistors for all the
linear regulators/switching elements is package selection for
efficient removal of heat. The power dissipated in a linear
regulator/switching element is
P_LINEAR = I_O × (V_IN – V_OUT)
Select a package and heatsink that maintains the junction
temperature below the rating with the maximum expected
ambient temperature.
Q1
The active element on the 2.5V/3.3V_MEM output has
different requirements for each of the two voltage settings. In
2.5V systems utilizing RDRAM (or voltage-compatible)
memory, Q1 has to be a bipolar NPN capable of conducting
up to 7.5A and exhibit a current gain (h_fe) of minimum 40 at
this current and 0.7V V_CE; in such systems the 2.5V output
is actively regulated while in active state. In 3.3V systems
(SDRAM or compatible) Q1 has to be an N-Channel
MOSFET; in such systems the MOSFET is switched on
during active state (S0, S1). The main criteria for the
selection of this transistor is output voltage budgeting. The
maximum r_DS(ON) allowed at highest junction temperature
can be expressed with the following equation:
r_DS(ON)max
=
V_{-----I--N----m-----i-n-----–----}V_{----O-----U----T----m----i--n-}
I_OUTmax
, where
V_INmin - minimum input voltage
V_OUTmin - minimum output voltage allowed
I_OUTmax - maximum output current
The gate bias available for this MOSFET is of the order of 8V.
Q5
If a P-Channel MOSFET is used to switch the 5VSB output
of the ATX supply into the 5V_DUAL output during S3 and S5
states (as dictated by EN5VDL status), then, similar to the
situation where Q1 is a MOSFET, the selection criteria of
this device is also proper voltage budgeting. The maximum
r_DS(ON), however, has to be achieved with only 4.5V of V_GS,
so a logic level MOSFET needs to be selected. If a PNP
device is chosen to perform this function, it has to have a low
saturation voltage while providing the maximum sleep
current and have a current gain sufficiently high to be
saturated using the minimum drive current (typically 20mA).
Q3,4
The two N-Channel MOSFETs are used to switch the 3.3V
and 5V inputs provided by the ATX supply into the
3.3VDUAL and 5VDUAL outputs, respectively, while in
active (S0, S1) state. Similar r_DS(ON) criteria apply in these
cases as well. Unlike the PMOS, however, these NMOS
transistors get the benefit of an increased V_GS drive
(approximately 8V and 7V, respectively).
Q2
The NPN transistor used as sleep state pass element (Q2)
on the 3.3V_DUAL output has to have a minimum current gain
of 100 at 1.5V V_CE and 500mA I_CE throughout the in-circuit
operating temperature range.
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