X9271_11 Datasheet, PDF (8/22 Pages) Intersil Corporation – Single, Digitally Controlled (XDCP™) Potentiometer

X9271
DEVICE DESCRIPTION
Instructions
IDENTIFICATION BYTE (ID AND A)
The first byte sent to the X9271 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier. The ID[3:0]
bit is the device ID for the X9271; this is fixed as
0101[B] (Table 4).
The A1 - A0 bits in the ID byte are the internal slave
address. The physical device address is defined by
the state of the A1 - A0 input pins. The slave address
is externally specified by the user. The X9271
compares the serial data stream with the address
input state; a successful compare of both address bits
is required for the X9271 to successfully continue the
command sequence. Only the device for which slave
address matches the incoming device address sent by
the master executes the instruction. The A1 - A0
inputs can be actively driven by CMOS input signals or
tied to V_CC or V_SS.
INSTRUCTION BYTE (I[3:0])
The next byte sent to the X9271 contains the
instruction and register pointer information. The three
most significant bits are used to provide the instruction
operation code (I[3:0]). The RB and RA bits point to
one of the four Data Registers. P0 is the POT
selection; since the X9271 is single POT, P0 = 0. The
format is shown in Table 7.
REGISTER BANK SELECTION (R1, R0, P1, P0)
There are 16 registers organized into four banks.
Bank 0 is the default bank of registers. Only Bank 0
registers can be used for the data register to Wiper
Counter Register operations.
Banks 1, 2, and 3 are additional banks of registers (12
total) that can be used for SPI write and read
operations. The data registers in Banks 1, 2, and 3
cannot be used for direct read/write operations to the
Wiper Counter Register (Tables 5 and 6).
TABLE 4. IDENTIFICATION BYTE FORMAT
DEVICE TYPE IDENTIFIER
ID3 ID2 ID1 ID0
0
1
0
1
(MSB)
SET TO 0 FOR
PROPER
OPERATION
0
0
INTERNAL
SLAVE
ADDRESS
A1
A0
(LSB)
TABLE 5. REGISTER SELECTION (DR0 TO DR3) TABLE
REGISTER
RB RA SELECTION
OPERATIONS
00
0
Data Register Read and Write; Wiper
Counter Register Operations
01
1
Data Register Read and Write; Wiper
Counter Register Operations
10
2
Data Register Read and Write; Wiper
Counter Register Operations
11
3
Data Register Read and Write; Wiper
Counter Register Operations
TABLE 6. REGISTER BANK SELECTION (BANK 0 TO BANK 3)
BANK
P1 P0 SELECTION
OPERATIONS
00
0
Data Register Read and Write; Wiper
Counter Register Operations
01
1
Data Register Read and Write Only
10
2
Data Register Read and Write Only
11
3
Data Register Read and Write Only
TABLE 7. INSTRUCTION BYTE FORMAT
INSTRUCTION OPCODE
I3
I2
I1
P0
(MSB)
NOTE:
5. Set to P0 = 0 for potentiometer operations.
REGISTER
SELECTION
RB
RA
REGISTER BANK SELECTION FOR
SP1 REGISTER WRITE AND READ OPERATIONS)
POTENTIOMETER SELECTION
(WCR SELECTION) (Note 5)
P1
P0
(LSB)
8
FN8174.3
June 23, 2011