LP3929 Datasheet, PDF (8/14 Pages) National Semiconductor (TI) – High Speed Bi-Directional Level Shifter and Ultra Low-Dropout CMOS Voltage Regulator and Line

LDO Electrical Characteristics
Unless otherwise specified: C_VBAT = 1 µF, I_OUT = 1 mA, C_VDDB = 1 µF, C_VDDA = 1 µF. Typical values and limits appearing in standard
typeface apply for T_A = 25°C. Limits appearing in boldface type apply over the entire ambient temperature range for operation,
−30°C to +85°C. (Note 3)
Symbol
Parameter
Conditions
Min Typ Max Units
V_OUT
ΔV_OUT
PSRR
Output Voltage, V_OUT = V_DDB
Output Voltage Tolerance
Line Regulation Error (Note 6)
Load Regulation Error (Note 7)
Output AC Line Regulation
Power Supply Rejection Ratio (Note
15)
ΔV_DO
Dropout Voltage (Note 8)
I_SC
T_ON
ρn (1/f)
Short Circuit Current Limit
Turn-On Time (Notes 9, 15)
Output Noise Density
e_n
Output
Capacitor
Output Noise Voltage
Output Filter Capacitance (Note 10)
Output Filter Capacitance ESR (Note
11)
Thermal Thermal Shutdown Temperature
Shutdown (Notes 12, 15)
Thermal Shutdown Hysteresis (Note
15)
I_OUT = 200mA, V_BAT = 3.05V to 5.5V
I_OUT = 1 mA
2.76
−2
−3
V_BAT = (V_OUT(nom) + 0.5V) to 5.5V, I_OUT = 1 mA
I_OUT = 1 mA to 200 mA
V_BAT = V_OUT(nom) + 1V,
I_OUT = 100 mA, C_OUT = 1.0 µF
V_BAT = V_OUT(nom) + 1V,
f = 1 kHz, I_OUT = 50 mA
V_BAT = V_OUT(nom) + 1V,
f = 10 kHz, I_OUT = 50 mA
I_OUT = 1 mA
I_OUT = 50 mA
I_OUT = 100 mA
I_OUT = 200 mA
V_BAT = 5.5V, Output Grounded (Steady State)
−0.15
−0.01
f = 1 kHz, C_OUT = 1.0 µF
BW = 10 Hz to 100 kHz, C_OUT = 1.0 µF
V_BAT = 3.05V to 5.5V,
0.7
I_OUT = 1mA to 200 mA
V_BAT = 3.05V to 5.5V,
5
I_OUT = 1mA to 200mA
V_BAT = 3.05V to 5.5V,
I_OUT = 1mA to 200mA
2.85
1.5
40
30
1
20
35
60
750
30
0.6
45
1.0
160
20
2.93
2
3
0.15
0.01
V
% of
V_OUT(nom)
%/V
%/mA
mV_PP
dB
mV
110
mA
200
µs
µV/√Hz
µVrms
22
µF
500
mΩ
°C
°C
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation.
Note 2: IEC61000-4-2 level 4 ESD tolerance applies to VDDB, D0_B–D3_B, CMD_B, CLK_B, WP and CP pins only. Device is tested in application (common
ground, bypass capacitors of 1.0 µF present on V_BAT, V_DDA and V_DDB).
Note 3: Typical values are given for V_DDA = 1.8V, V_BAT = 3.6V, T_A = 25°C
Note 4: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are reference to ground unless otherwise
specified.
Note 5: Input signal for test purpose is defined as: A side – 0V to 1.8V with 2ns rise time (20%-70%) and B side – 0V to 2.85V with 2ns rise time (20%-70%)
Note 6: The output voltage changes slightly with line voltage. An increase in the line voltage results in a slight increase in the output voltage and vice versa.
Note 7: The output voltage changes slightly with load current. An increase in the load current results in a slight decrease in the output voltage and vice versa.
Note 8: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply
for input voltages below 2.7V.
Note 9: Turn-on time is that between when the enable input is high an the output voltage just reaching 95% of its nominal value.
Note 10: Range of capacitor value for which the device will remain stable. This electrical specification is guaranteed by design.
Note 11: Range of capacitor ESR values for which the device will remain stable. This electrical specification is guaranteed by design.
Note 12: The built-in thermal shut-down of the LDO is also used to put all A and B outputs in tri-state mode.
Note 13: Additional information on lead temperature and pad temperature can be found in National Semiconductor Application Note (AN-1112).
Note 14: Unused inputs must be terminated.
Note 15: This electrical specification is guaranteed by design.
Note 16: The SD/MMC card specification calls for a total of 30 pF capacitance. A load of 15 pF is internal to the LP3929, so the external load capacitance on the
B side should comprise the remaining (15 pF or less).
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