LP2998 Datasheet, PDF (8/18 Pages) Intersil Corporation – DDR-II and DDR-I Termination Regulator

Block Diagram
Description
The LP2998 is a linear bus termination regulator designed to
meet the JEDEC requirements of SSTL-2 and SSTL-18. The
output, V_TT is capable of sinking and sourcing current while
regulating the output voltage equal to VDDQ / 2. The output
stage has been designed to maintain excellent load regulation
while preventing shoot through. The LP2998 also incorpo-
rates two distinct power rails that separates the analog cir-
cuitry from the power output stage. This allows a split rail
approach to be utilized to decrease internal power dissipation.
It also permits the LP2998 to provide a termination solution
for the next generation of DDR-SDRAM memory (DDRII). The
LP2998 can also be used to provide a termination voltage for
other logic schemes such as SSTL-3 or HSTL.
Series Stub Termination Logic (SSTL) was created to im-
prove signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent
data error from signal reflections while transmitting at high
frequencies encountered with DDR-SDRAM. The most com-
mon form of termination is Class II single parallel termination.
This involves one R_S series resistor from the chipset to the
memory and one R_T termination resistor. Typical values for
R_S and R_T are 25 Ohms, although these can be changed to
scale the current requirements from the LP2998. This imple-
mentation can be seen below in .
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FIGURE 1. SSTL-Termination Scheme
Pin Descriptions
AVIN AND PVIN
AVIN and PVIN are the input supply pins for the LP2998. AVIN
is used to supply all the internal control circuitry. PVIN, how-
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ever, is used exclusively to provide the rail voltage for the
output stage used to create V_TT. These pins have the capa-
bility to work off separate supplies, under the condition that
AVIN is always greater than or equal to PVIN. For SSTL-18
applications, it is recommended to connect PVIN to the 1.8V
rail used for the memory core and AVIN to a rail within its
operating range of 2.2V to 5.5V (typically a 2.5V supply). PVIN
should always be used with either a 1.8V or 2.5V rail. This
prevents the thermal limit from tripping because of excessive
internal power dissipation. If the junction temperature ex-
ceeds the thermal shutdown than the part will enter a shut-
down state identical to the manual shutdown where V_TT is tri-
stated and V_REF remains active. A lower rail such as 1.5V can
be used but it will reduce the maximum output current, there-
fore it is not recommended for most termination schemes.
VDDQ
VDDQ is the input used to create the internal reference volt-
age for regulating V_TT. The reference voltage is generated
from a resistor divider of two internal 50kΩ resistors. This
guarantees that V_TT will track VDDQ / 2 precisely. The optimal
implementation of VDDQ is as a remote sense. This can be
achieved by connecting VDDQ directly to the 1.8V rail at the
DIMM instead of PVIN. This ensures that the reference volt-
age tracks the DDR memory rails precisely without a large
voltage drop from the power lines. For SSTL-18 applications
VDDQ will be a 1.8V signal, which will create a 0.9V termina-
tion voltage at V_TT (See Electrical Characteristics Table for
exact values of V_TT over temperature).
V_SENSE
The purpose of the sense pin is to provide improved remote
load regulation. In most motherboard applications the termi-
nation resistors will connect to V_TT in a long plane. If the output
voltage was regulated only at the output of the LP2998 then
the long trace will cause a significant IR drop resulting in a
termination voltage lower at one end of the bus than the other.
The V_SENSE pin can be used to improve this performance, by
connecting it to the middle of the bus. This will provide a better
distribution across the entire termination bus. If remote load
regulation is not used then the V_SENSE pin must still be con-
nected to V_TT. Care should be taken when a long V_SENSE trace
is implemented in close proximity to the memory. Noise pick-
up in the V_SENSE trace can cause problems with precise
regulation of V_TT. A small 0.1uF ceramic capacitor placed next
to the V_SENSE pin can help filter any high frequency signals
and preventing errors.
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