LP2998 Datasheet, PDF (15/18 Pages) Intersil Corporation – DDR-II and DDR-I Termination Regulator

PCB Layout Considerations
1. The input capacitor for the power rail should be placed
as close as possible to the PVIN pin.
2. V_SENSE should be connected to the V_TT termination bus
at the point where regulation is required. For
motherboard applications an ideal location would be at
the center of the termination bus.
3. V_DDQ can be connected remotely to the V_DDQ rail input at
either the DIMM or the Chipset. This provides the most
accurate point for creating the reference voltage.
4. For improved thermal performance excessive top side
copper should be used to dissipate heat from the
package. Numerous vias from the ground connection to
the internal ground plane will help. Additionally these can
be located underneath the package if manufacturing
standards permit.
5. Care should be taken when routing the V_SENSE trace to
avoid noise pickup from switching I/O signals. A 0.1uF
ceramic capacitor located close to the _SENSE can also be
used to filter any unwanted high frequency signal. This
can be an issue especially if long _SENSE traces are used.
6. V_REF should be bypassed with a 0.01 µF or 0.1 µF
ceramic capacitor for improved performance. This
capacitor should be located as close as possible to the
V_REF pin.
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