ISL6537ACRZ-T Datasheet, PDF (8/16 Pages) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems

ISL6537A
FB2 (Pin 18)
Connect the output of the V_{TT_GMCH/CPU} linear regulator to
this pin through a properly sized resistor divider. The voltage
at this pin is regulated to 0.8V. This pin is monitored for
undervoltage events.
DRIVE2 (Pin 10)
This pin provides the gate voltage for the V_{TT_GMCH/CPU}
linear regulator pass transistor. Connect this pin to the gate
terminal of an external N-Channel MOSFET transistor.
FB3 (Pin 18)
Connect the output of the DAC linear regulator to this pin
through a properly sized resistor divider. The voltage at this
pin is regulated to 0.8V.
DRIVE3 (Pin 10)
This pin provides the gate voltage for the DAC linear
regulator pass transistor. Connect this pin to the gate
terminal of an external N-Channel MOSFET transistor.
VIDPGD (Pin 12)
The VIDPGD pin is an open-drain logic output that changes
to a logic low if the V_{TT_GMCH/CPU} linear regulator is out of
regulation in S0/S1/S2 state. VIDPGD will always be low in
any state other than S0/S1/S2.
SLP_S5# (Pin 23)
This pin accepts the SLP_S5# sleep state signal.
SLP_S3# (Pin 2)
This pin accepts the SLP_S3# sleep state signal.
Functional Description
Overview
The ISL6537A provides complete control, drive, protection
and ACPI compliance for regulator powering DDR memory
systems and the GMCH core and GMCH/CPU termination
rails. It is primarily designed for computer applications
powered from an ATX power supply.
A 250kHz Synchronous Buck Regulator with a precision
0.8V reference provides the proper Core voltage to the
system memory of the computer. An internal LDO regulator
with the ability to both sink and source current and an
externally available buffered reference that tracks the V_DDQ
output by 50% provides the V_TT termination voltage.
A second 250kHz PWM Buck regulator, which requires an
external MOSFET driver, provides the GMCH core voltage.
This PWM regulator is +180° out of phase with the PWM
regulator used for the Memory core. Two additional LDO
controllers are included, one for the regulation of the
GMCH/CPU termination rail and the second for the DAC.
ACPI compliance is realized through the SLP_S3 and
SLP_S5 sleep signals and through monitoring of the 12V
ATX bus.
Initialization
The ISL6537A automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltages. The POR monitors
the bias voltage at the 5VSBY and P12V pins. The POR
function initiates soft-start operation after the bias supply
voltages exceed their POR thresholds.
ACPI State Transitions
Figure 1 shows how the individual regulators are controlled
during all state transitions. All references to timing in this
section are in reference to Figure 1.
Cold Start (S4/S5 to S0 Transition)
At the onset of a mechanical start, time t₀ in Figure 1, the
ISL6537A receives its bias voltage from the 5V Standby bus
(5VSBY). Once the 5VSBY rail has exceeded the POR
threshold, the ISL6537A will remain in an internal S5 state
until both the SLP_S3 and SLP_S5 signal have transitioned
high and the 12V POR threshold has been exceeded by the
+12V rail from the ATX, which occurs at time t₁.
Once all of these conditions are met, the PWM error
amplifiers will first be reset by internally shorting the COMP
pins to the respective FB pins. This reset lasts for three soft-
start cycles, which is typically 24ms (one soft-start cycle is
typically 8.2ms). The digital soft-start sequence will then
begin. Each regulator is enabled and soft-started according
to a preset sequence.
At time t₂, the 3 soft-start cycle reset has ended and the
V_{DDQ_DDR} rail is digitally soft-started.
The digital soft-start for both PWM regulators is accomplished
by clamping the error amplifier reference input to a level
proportional to the internal digital soft-start voltage. As the soft-
start voltage slews up, the PWM comparator generates PHASE
pulses of increasing width that charge the output capacitor(s).
This method provides a rapid and controlled output voltage rise.
The linear regulators, with the exception of the internal
V_{TT_DDR} LDO, are soft-started in a similar manner. The
error amplifier reference is clamped to the internal digital
soft-start voltage. As the soft-start voltage ramps up, the
respective DRIVE pin voltages increase, thus enhancing the
N-MOSFETs and charging the output capacitors in a
controlled manner.
At time t₃, the V_{DDQ_DDR} rail is in regulation and the
V_GMCH rail is soft-started. At time t₄, the V_GMCH rail is in
regulation and the V_{TT_GMCH/CPU} and the DAC linear
regulators are soft-started. At time t₅, the V_{TT_GMCH/CPU}
rail and DAC rails are in regulation and the V_{TT_DDR} internal
regulator is soft-started.
The V_{TT_DDR} LDO soft-starts in a manner unlike the other
regulators. When the V_{TT_DDR} regulator is disabled, the
reference is internally shorted to the V_{TT_DDR} output. This
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