ISL6537ACRZ-T Datasheet, PDF (1/16 Pages) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems

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Data Sheet
July 18, 2007
ISL6537A
FN9143.5
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6537A provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
supply V_DDQ during S0/S1 and S3 states. During S0/S1 state,
a fully integrated sink-source regulator generates an accurate
(V_DDQ/2) high current V_TT voltage without the need for a
negative supply. A buffered version of the V_DDQ/2 reference is
provided as V_REF. A second PWM controller, which requires
external MOSFET drivers, is available for regulation of the
GMCH Core voltage. An LDO controller is also integrated for
the CPU V_TT termination voltage regulation and the DAC.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
±2% over line, load, and temperature ranges. The output is
user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
indicates that the GMCH and CPU V_TT termination voltage
is within spec and operational.
All outputs, except VDAC, have undervoltage protection.
The switching regulator also has overvoltage and
overcurrent protection. Thermal shutdown is integrated.
Pinout
ISL6537A (6X6 QFN)
TOP VIEW
28 27 26 25 24 23 22
5VSBY 1
21 DRIVE3
S3# 2
P12V 3
GND 4
DDR_VTT 5
GND
29
20 FB3
19 PWM4
18 FB4
17 COMP4
DDR_VTT 6
16 COMP
VDDQ 7
15 FB
8 9 10 11 12 13 14
Features
• Generates 5 Regulated Voltages
- Synchronous Buck PWM Controller for DDR V_DDQ
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference for DDR V_TT
- PWM Regulator for GMCH Core
- LDO Regulator for CPU/GMCH V_TT Termination
- LDO Regulator for DAC
• ACPI Compliant Sleep State Control
• Glitch-Free Transitions During State Changes
• Integrated V_REF Buffer
• V_DDQ PWM Controller Drives Low Cost N-Channel
MOSFETs
• 250kHz Constant Frequency Operation
- Both PWM Controllers are Phase Shifted 180°
• Tight Output Voltage Regulation
- All Outputs: ±2% Over Temperature
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V Supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Overvoltage Monitoring
• OCP on the V_DDQ Switching Regulator
• Integrated Thermal Shutdown Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• _{Single and Dual Channel DDR Memory Power Systems in}
ACPI Compliant PCs
• _{Graphics Cards - GPU and Memory Supplies}
• ASIC Power Supplies
• Embedded Processor and I/O Supplies
• DSP Supplies
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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