ISL6524A Datasheet, PDF (8/16 Pages) Intersil Corporation – VRM8.5 PWM and Triple Linear Power System Controller

10V
0V
3.0V
ATX 12V
ATX 5V
SS24
VTTPG
SS13
PGOOD
ATX 3.3V
V_OUT4 (1.8V)
V_OUT1 (1.65V)
V_OUT3 (1.5V)
V_OUT2 (1.2V)
0V
T0 T1
T2 T3 T4 T5
TIME
FIGURE 6. SOFT-START INTERVAL
The T2 to T3 time interval is dependent upon the value of
C_SS13. The same capacitor is also responsible for the ramp-
up time of the OUT1 and OUT3 voltages. If selecting a
different capacitor then recommended in the circuit application
literature, consider the effects the different value will have on
the ramp-up time and inrush currents of the OUT1 and OUT3
outputs.
Fault Protection
All four outputs are monitored and protected against extreme
overload. The chip’s response to an output overload is
selective, depending on the faulting output.
An over-voltage on V_OUT1 output (VSEN1) disables outputs
1, 2, and 3, and latches the IC off. An under-voltage on
V_OUT4 output latches the IC off. A single over-current event
on output 1, or an under-voltage event on output 2 or 3,
increments the respective fault counters and triggers a
shutdown of outputs 1, 2, and 3, followed by a soft-start re-
start. After three consecutive fault events on either counter,
the chip is latched off. Removal of bias power resets both the
fault latch and the counters. Both counters are also reset by
a successful start-up of all the outputs.
Figure 7 shows a simplified schematic of the fault logic. The
over-current latches are set dependent upon the states of
the over-current (OC1), output 2 and 3 under-voltage (UV2,
UV3) and the soft-start signals (SS13, SS24). Window
comparators monitor the SS pins and indicate when the
respective C_SS pins are fully charged to above 4.0V (UP
8
signals). An under-voltage on either linear output (VSEN2,
VSEN3, or VSEN4) is ignored until the respective UP signal
goes high. This allows V_OUT3 and V_OUT4 to increase
without fault at start-up. Following an over-current event
(OC1, UV2, or UV3 event), bringing the SS24 pin below 0.8V
resets the over-current latch and generates a soft-started
ramp-up of the outputs 1, 2, and 3.
SS13UP
UV3
OC1
4V
SS13
0.8V
SS24
4V
OV
UV4
OC
LATCH
SQ
R
COUNTER
R
INHIBIT1,2,3
SSDOWN
SS24UP
POR
R
FAULT
LATCH
SQ
RQ
FAULT
R
COUNTER
UV2
SQ
OC
LATCH
FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC
OUT1 Over-Voltage Protection
During operation, a short across the PWM upper MOSFET
(Q1) causes V_OUT1 to increase. When the output exceeds
the over-voltage threshold of 120% of DACOUT, the over-
voltage comparator trips to set the fault latch and turns the
lower MOSFET (Q2) on as needed to regulate the output
voltage to the 120% threshold. This operation typically
results in the blow of the input fuse, subsequent discharge of
V_OUT1.
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), the output level
is monitored for voltages above 1.3V. Should VSEN1 exceed
this level, the lower MOSFET, Q2, is driven on.
Over-Current Protection
All outputs are protected against excessive over-currents.
The PWM controller uses the upper MOSFET’s on-
resistance, r_DS(ON) to monitor the current for protection
against a shorted output. All linear regulators monitor their
respective VSEN pins for under-voltage to protect against
excessive currents.
Figure 8 illustrates the over-current protection with an
overload on OUT1. The overload is applied at T0 and the
FN9064.1
April 8, 2005