ISL6522A Datasheet, PDF (8/13 Pages) Intersil Corporation – Buck and Synchronous Rectifier Pulse-Width Modulator (PWM) Controller

ISL6522A
BOOT
D1
C_BOOT
ISL6522A
PHASE
SS
+12V
C_SS
GND
VCC
C_VCC
+V_IN
Q1 _LO
V_OUT
Q2 ^CO
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous rectified buck converter. The output voltage
(V_OUT) is regulated to the reference voltage level. The error
amplifier (error amp) output (V_E/A) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V_IN at the
PHASE node. The PWM wave is smoothed by the output filter
(L_O and C_O).
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A. This function is dominated by a DC
gain and the output filter (L_O and C_O), with a double pole
break frequency at F_LC and a zero at F_ESR. The DC gain of
the modulator is simply the input voltage (V_IN) divided by the
peak-to-peak oscillator voltage ∆V_OSC.
Modulator Break Frequency Equations
F_LC=
------------------¹--------------------
2π • L_O • C_O
F_ESR=
----------------------¹----------------------
2π • (ESR • C_O)
The compensation network consists of the error amplifier
(internal to the ISL6522A) and the impedance networks Z_IN
and Z_FB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f_0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f_0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
F_Z1
=
----------------¹------------------
2π • R2 • C1
F_Z2 = ₂----_π-----_•----₍---_R-----₁----+-¹----_R-----₃----₎---_•-----_C----₃--
F_P1
=
--------------------------¹----------------------------
2
π
•
R
2
•


C^-C----1^{-1----+•-----CC----2-}2^{--}
F_P2
=
----------------¹------------------
2π • R3 • C3
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1^ST Zero Below Filter’s Double Pole
(~75% F_LC)
OSC
V_IN
DRIVER
PWM
COMPARATOR
L_O
V_OUT
∆V_OSC
-
+
DRIVER
PHASE
C_O
ESR
(PARASITIC)
Z_FB
V_E/A
-
+
Z_IN
ERROR ^REFERENCE
AMP
DETAILED COMPENSATION COMPONENTS
C2
C1
R2
Z_FB
V_OUT
Z_IN
C3 R3
R1
COMP
ISL6522A
FB
-
+
REF
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
3. Place 2^ND Zero at Filter’s Double Pole
4. Place 1^ST Pole at the ESR Zero
5. Place 2^ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F_P2 with the capabilities of the error
amplifier. The closed loop gain is constructed on the log-log
graph of Figure 8 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
8
FN9122.2
April 13, 2005