ISL6522A Datasheet, PDF(10/13 Page) Intersil Corporation – Buck and Synchronous Rectifier Pulse-Width Modulator (PWM) Controller

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ISL6522A Datasheet, PDF (10/13 Pages) Intersil Corporation – Buck and Synchronous Rectifier Pulse-Width Modulator (PWM) Controller

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ISL6522A

should be at least 1.25 times greater than the maximum

input voltage and a voltage rating of 1.5 times is a

conservative guideline. The RMS current rating requirement

for the input capacitor of a buck regulator is approximately

1/2 the DC load current.

For a through-hole design, several electrolytic capacitors

(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX

or equivalent) may be needed. For surface mount designs,

solid tantalum capacitors can be used, but caution must be

exercised with regard to the capacitor surge current rating.

These capacitors must be capable of handling the surge-

current at power-up. The TPS series available from AVX, and

the 593D series from Sprague are both surge current tested.

MOSFET Selection/Considerations

The ISL6522A requires two N-Channel power MOSFETs.

These should be selected based upon rDS(ON), gate supply

requirements, and thermal management requirements.

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss

components; conduction loss and switching loss. The

conduction losses are the largest component of power

dissipation for both the upper and the lower MOSFETs.

These losses are distributed between the two MOSFETs

according to duty factor. The switching losses seen when

sourcing current will be different from the switching losses seen

when sinking current. When sourcing current, the upper

MOSFET realizes most of the switching losses. The lower

switch realizes most of the switching losses when the converter

is sinking current (see the equations below).

Losses while Sourcing Current

PUPPER

(

)

1--

PLOWER = Io2 x rDS(ON) x (1 - D)

Losses while Sinking Current

PUPPER = Io2 x rDS(ON) x D

PLOWER

Io2

rDS(ON)

1--

VIN

tSW

Where: D is the duty cycle = VOUT / VIN,

tSW is the switching interval, and

FS is the switching frequency.

These equations assume linear voltage-current transitions and

do not adequately model power loss due the reverse-recovery

of the upper and lower MOSFETâs body diode. The

gate-charge losses are dissipated by the ISL6522A and do not

heat the MOSFETs. However, large gate-charge increases the

switching interval, tSW which increases the upper MOSFET

switching losses. Ensure that both MOSFETs are within their

maximum junction temperature at high ambient temperature by

calculating the temperature rise according to package thermal-

resistance specifications. A separate heatsink may be

necessary depending upon MOSFET power, package type,

ambient temperature and air flow.

Standard-gate MOSFETs are normally recommended for

use with the ISL6522A. However, logic-level gate MOSFETs

can be used under special circumstances. The input voltage,

upper gate drive level, and the MOSFETs absolute gate-to-

source voltage rating determine whether logic-level

MOSFETs are appropriate.

Figure 9 shows the upper gate drive (BOOT pin) supplied by

a bootstrap circuit from VCC . The boot capacitor, CBOOT

develops a floating supply voltage referenced to the PHASE

pin. This supply is refreshed each cycle to a voltage of VCC

less the boot diode drop (VD) when the lower MOSFET, Q2

turns on. A logic-level MOSFET can only be used for Q1 if

the MOSFETs absolute gate-to-source voltage rating

exceeds the maximum voltage applied to VCC. For Q2, a

logic-level MOSFET can be used if its absolute gate-to-

source voltage rating exceeds the maximum voltage applied

to PVCC.

+12V

DBOOT

VCC

+5V OR +12V

ISL6522A

BOOT

UGATE

CBOOT

PHASE

NOTE:

VG-S â VCC - VD

+5V

PVCC OR +12V

LGATE

PGND

NOTE:

VG-S â PVCC

GND

FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION

+12V

VCC

+5V OR LESS

ISL6522A

BOOT

UGATE

PHASE

+5V

PVCC OR +12V

LGATE

PGND

NOTE:

VG-S â VCC - 5V

NOTE:

VG-S â PVCC

GND

FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION

Figure 10 shows the upper gate drive supplied by a direct

connection to VCC. This option should only be used in

converter systems where the main input voltage is +5VDC or

less. The peak upper gate-to-source voltage is approximately

FN9122.2

April 13, 2005

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