ISL6521 Datasheet, PDF (8/13 Pages) Intersil Corporation – PWM Buck DC-DC and Triple Linear Power Controller

ISL6521
OSC
∆ V_OSC
V_IN
DRIVER1
PWM
COMP
-
+
Z_FB
SYNC
DRIVER
L_O
PHASE
V_OUT
C_O ⁺
ESR
(PARASITIC)
V_E/A
+
ERROR
AMP
Z_IN
0.8V
DETAILED COMPENSATION COMPONENTS
C2
C1 _R2
Z_FB
V_OUT
Z_IN
C3 _R3
COMP
R_S1
FB
-
+
R_P1
ISL6521
0.8V
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
and Z_FB. The goal of the compensation network is to provide
a closed loop transfer function with high 0dB crossing
frequency (f_0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f_0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1 , R2 ,
R3 , C1 , C2 , and C3) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1^ST Zero Below Filter’s Double Pole (~75% F_LC)
3. Place 2^ND Zero at Filter’s Double Pole
4. Place 1^ST Pole at the ESR Zero
5. Place 2^ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
F_Z1
=
-----------------¹------------------
2π × R2 × C1
F_Z2 = ₂----_π-----_×-----₍--_R-----_S----₁---¹-+-----_R-----₃----₎---_×-----_C-----₃--
F_P1
=
---------------------------¹---------------------------
2
π
×
R₂
×


C^-C----11^{-----+×-----CC-----22--}
F_P2
=
-----------------¹------------------
2π × R3 × C3
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high
gain peak dependent on the quality factor (Q) of the output
filter, which is not shown in Figure 5. Using the above
guidelines should yield a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F_P2
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the log-log graph of Figure 6 by
adding the Modulator Gain (in dB) to the Compensation Gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
F_Z1
F_Z2 F_P1 F_P2
OPEN LOOP
100
ERROR AMP GAIN
80
20
log



V^--V---_P^-I--N-_P^---_{}
60
40
COMPENSATION
GAIN
20
0
-20
20
log



-_R-^R----_S--²--₁--_{}
MODULATOR
-40
GAIN
F_LC F_ESR
-60
10
100
1K
10K 100K
FREQUENCY (Hz)
CLOSED LOOP
GAIN
1M 10M
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Individual Output Disable
The PWM and linear controllers can independently be
shutdown.
To disable the switching regulator, use an open-drain or
open-collector device capable of pulling the OCSET pin (with
the attached R_OCSET pull-up) below 1.25V. To minimize the
possibility of OC trips at levels different than predicted, a
C_OCSET capacitor with a value of an order of magnitude
larger than the output capacitance of the pull-down device,
has to be used in parallel with R_OCSET (1nF recommended).
Upon turn-off of the pull-down device, the switching regulator
undergoes a soft-start cycle.
To disable a particular linear controller, pull and hold the
respective FB pin above a typical threshold of 1.25V. One
way to achieve this task is by using a logic gate coupled
8