ISL6521 Datasheet, PDF (6/13 Pages) Intersil Corporation – PWM Buck DC-DC and Triple Linear Power Controller

ISL6521
the clamped error amplifier output voltage. As the internal
soft-start voltage increases, the pulse-width on the PHASE
pin increases to reach its steady-state duty cycle at time T2.
Also at time T2, the error amplifier references of the linear
controllers, ramp to their final value bringing all outputs
within regulation limits.
three soft-start periods, the fourth cycle initiates a ramp-up of
this linear output at time T3. One soft-start period after T3,
the linear output is within regulation limits. UV glitches less
than 1µs (typically) in duration are ignored.
V_OUT4 (3.3V)
+5V
0V
(1V/DIV)
V_OUT4 (3.3V)
V_OUT2 (2.5V)
V_OUT3 (1.8V)
V_OUT1 (1.5V)
(0.5V/DIV.)
0V
V_OUT3 (1.8V)
V_OUT1 (1.5V)
V_OUT2 (2.5V)
SOFT-START
FUNCTION
UV MONITORING
0V
(0.5V/DIV)
T0 T1
T2
TIME
FIGURE 1. SOFT-START INTERVAL
Overcurrent Protection
All outputs are protected against excessive overcurrents.
The PWM controller uses the upper MOSFET’s
on-resistance, r_DS(ON) to monitor the current for protection
against a shorted output. All linear controllers monitor their
respective FB pins for undervoltage events to protect against
excessive currents.
A sustained overload (undervoltage on linears or overcurrent
on the PWM) on any output results in an independent
shutdown of the respective output, followed by subsequent
individual re-start attempts performed at an interval equivalent
to 3 soft-start intervals. Figure 2 describes the protection
feature. At time T0, an overcurrent event sensed across the
switching regulator’s upper MOSFET (r_DS(ON) sensing)
triggers a shutdown of the V_OUT1 output. As a result, its
internal soft-start initiates a number of soft-start cycles. After a
three-cycle wait, the fourth soft-start initiates a ramp-up
attempt of the failed output, at time T2, bringing the output in
regulation at time T4.
To exemplify a UV event on one of the linears, at time T1,
the clock regulator (V_OUT2) is also subjected to an
overcurrent event, resulting in a UV condition. Similarly, after
6
V_OUT1
INACTIVE
V_OUT2
ACTIVE
T0
T1
TIME
T2
T3 T4
FIGURE 2. OVERCURRENT/UNDERVOLTAGE PROTECTION
RESPONSE
Overcurrent protection is performed on the synchronous
switching regulator on a cycle-by-cycle basis. OC monitoring
is active as long as the regulator is operational. Since the
overcurrent protection on the linear regulators is performed
through undervoltage monitoring at the feedback pins (FB2,
FB3, and FB4), this feature is activated approximately 25%
into the soft-start interval (see Figure 2).
A resistor (R_OCSET) programs the overcurrent trip level for
the PWM converter. As shown in Figure 3, the internal
40µA current sink (I_OCSET) develops a voltage across
R_OCSET (V_SET) that is referenced to V_IN . The DRIVE
signal enables the overcurrent comparator (OCC). When
the voltage across the upper MOSFET (V_DS(ON)) exceeds
V_SET, the overcurrent comparator trips to set the
overcurrent latch. Both V_SET and V_DS(ON) are referenced
to V_IN and a small capacitor across R_OCSET helps V_OCSET
track the variations of V_IN due to MOSFET switching. The
overcurrent function will trip at a peak inductor current
(I_PEAK) determined by:
I_PEAK
=
I--_{O-----C----S----E----T-----}×_{----R-----O----C-----S----E----T-}
r_DS(ON)