ISL6455 Datasheet, PDF (8/13 Pages) Intersil Corporation – Low shutdown supply current

ISL6455, ISL6455A
Pin Descriptions
PVCC - Positive supply for the power (internal FET) stage of
the PWM section.
SGND - Analog ground for the PWM. All internal control
circuits are referenced to this pin.
EN - The PWM controller is enabled when this pin is HIGH,
and disabled when the pin is pulled LOW. It is a CMOS
logic-level input (referenced to V_IN).
V_IN_LDO - This is the input voltage pin for LDO1 and LDO2.
EN_LDO - LDO1 and LDO2 are enabled when this pin is
HIGH, and disabled when the pin is pulled LOW. It is a
CMOS logic-level input (referenced to V_IN).
CT - Timing capacitor pin to set the 25ms minimum pulse
width for the RESET signal.
RESET - This pin is the output of the reset supervisory
circuit, which monitors VIN_PWM. The IC asserts a RESET
signal whenever the supply voltage drops below a preset
threshold. It is kept asserted for a minimum of 25ms after
V_CC (V_IN) has risen above the reset threshold. The output is
push-pull. The device will continue to operate until V_IN drops
below the UVLO threshold.
When EN = LOW then RESET = HIGH and the moment EN
is made HIGH the RESET will pulse LOW for a period of
25ms minimum (VIN > Reset threshold). If VIN < reset
threshold then it will switch low and stay low for a period of
25ms after VIN_PWM crosses the reset threshold.
PG_LDO - This is a high impedance open drain output that
provides the status of both LDOs. When either of the outputs
are out of regulation, PG_LDO goes LOW. Add a pull-up
resistor approximately 10k from PG_LDO to VIN.
CC1 - This is the compensation capacitor connection for
LDO1. Connect a 0.033µF capacitor from CC1 to
GND_LDO.
CC2 - This is the compensation capacitor connection for
LDO2. Connect a 0.033µF capacitor from CC2 to
GND_LDO.
V_OUT2 - This pin is the output of LDO2. Bypass with a
minimum 2.2µF, low ESR capacitor to GND_LDO for stable
operation.
GND_LDO - Ground pin for LDO1 and LDO2.
V_OUT1 - This pin is the output of LDO1. Bypass with a
minimum 2.2µF, low ESR capacitor to GND_LDO for stable
operation.
PGND - Power ground for the PWM controller stage.
V_OUT - This I/O pin senses the output voltage of the PWM
converter for the purpose of detecting the over and
undervoltage conditions.
PG_PWM - This pin is an active pull-down able to sink 1mA
(min). This output is HIGH IMPEDANCE when V_OUT is
within ±8% (typical). For pull-up, add a resistor
approximately 10k from PG_PWM to VIN
FB_LDO1 and FB_LDO2 - These pins are used to set the
LDO output with the proper selection of resistors. i.e. Ra and
Rb for LDO1 and Rc and Rd for LDO2. Resistors should be
chosen to provide a minimum current of 200µA load for each
LDO output.
LX - The LX pin is the switching node of synchronous buck
converter, connected internally at the junction point of the
upper MOSFET source and lower MOSFET drain. Connect
this pin to the output inductor.
V_IN - This pin is the power supply for the PWM controller
stage and must be closely decoupled to ground.
SYNC - This is the external clock synchronization input. The
device can be synchronized to 500kHz to 1MHz switching
frequency. If unused then it should be tied to GND or VCC
GND - Tie this pin to the ground plane with a low impedance,
shortest possible path.
FB_PWM- This is used to set the value of the output voltage
of the PWM with external resistors Re and Rf.
8
FN9196.1
February 19, 2014