ISL6455 Datasheet, PDF (6/13 Pages) Intersil Corporation – Low shutdown supply current

ISL6455, ISL6455A
Electrical Specifications
Recommended operating conditions unless otherwise noted. V_IN = V_IN_LDO = PV_CC = 3.3V for ISL6455 and
5.0V for the ISL6455A, Compensation Capacitors = 33nF for LDO1 and LDO2. T_A = -40°C to +85° (Note 2),
typical values are at T_A = +25°C.Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless
otherwise specified. Temperature limits established by characterization and are not production tested
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNITS
Output Voltage Noise (Note 6)
ENABLE (EN and (EN_LDO)
10Hz < f < 100kHz, I_OUT = 10mA
C_OUT = 2.2µF
C_OUT = 10µF
-
30
-
µV_RMS
-
20
-
µV_RMS
EN High Level Input Voltage
As % of VIN
70
-
-
%
EN Low Level Input Voltage
As % of VIN
-
-
30
%
RESET BLOCK SPECIFICATIONS
RESET (reset released)
RESET (reset asserted)
ISL6455, ISOURCE = 500µA, VIN = 2.90V
ISL6455, ISINK = 1.2mA, VIN = 2.50V
0.8 x
-
-
V
V_CC
-
-
0.3
V
RESET Rising Threshold
ISL6455
2.71 2.77 2.84
V
RESET Falling Threshold
ISL6455
2.69 2.75 2.81
V
RESET (reset released)
RESET (reset asserted)
ISL6455A, ISOURCE = 800µA, VIN = 4.70V
ISL6455A, ISINK = 3.2mA, VIN = 4.10V
0.8 x
-
-
V
V_CC
-
-
0.4
V
RESET Rising Threshold
ISL6455A
4.19 4.27 4.35
V
RESET Falling Threshold
ISL6455A
4.16 4.24 4.32
V
RESET Threshold Hysteresis
ISL6455
-
20
-
mV
RESET Threshold Hysteresis
ISL6455A
-
30
-
mV
RESET Active Timeout Period (Note 5)
POWER GOOD (PG_LDO)
C_T = 0.01µF
-
25
-
ms
Minimum Input Voltage for Valid PG_LDO
-
1.2
-
V
PGOOD Threshold (Rising)
PGOOD Threshold (Falling)
FB_LDO vs 1.184V VREF
+11
+15
+17
%
-17
-15
-11
%
PGOOD Output Voltage Low
PGOOD Output Leakage Current
I_OL = 1.2mA
PG_LDO = GND or VIN
-
-
0.4
V
-
0.01
0.1
µA
PWM OUTPUT OVERVOLTAGE
Overvoltage Threshold
FB_PWM vs 0.45V VREF
28
31
34
%
NOTES:
3. This is the V_IN current consumed when the device is active but not switching. Does not include gate drive current.
4. The dropout voltage is defined as V_IN - V_OUT, when V_OUT is 50mV below the value of V_OUT for V_IN = V_OUT + 0.5V.
5. The RESET timeout period is linear with CT at the slope of 2.5ms/nF. Thus, at 10nF (0.01µF) the RESET time is 25ms; at 1000nF (0.1µF) the
RESET time would be 250ms.
6. Limits established by characterization and are not production tested.
7. Add the external feedback resistor mismatch error to get initial V_OUT accuracy.
6
FN9196.1
February 19, 2014