ISL6432 Datasheet, PDF (8/12 Pages) Intersil Corporation – PWM and Triple Linear Power Controller for Home Gateway Applications

ISL6432
error amplifier (Error Amp) output (V_E/A) is compared with
the oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V_IN at the
PHASE node. The PWM wave is smoothed by the output
filter (L_O and C_O).
OSC
V_IN
DRIVER1
∆V_OSC
PWM
COMP
-
+
SYNC
DRIVER
L_O
PHASE
V_OUT
+
C_O
ESR
(PARASITIC)
Z_FB
V_E/A
+
ERROR
AMP
Z_IN
0.8V
DETAILED COMPENSATION COMPONENTS
C2
C1 _R2
Z_FB
V_OUT
Z_IN
C3 R3
COMP
R_S1
FB
-
+
R_P1
ISL6432
0.8V
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A. This function is dominated by a DC
Gain, given by V_IN/V_OSC, and shaped by the output filter, with
a double pole break frequency at F_LC and a zero at F_ESR.
Modulator Break Frequency Equations
F_LC=
-------------------¹--------------------
2π × L_O × C_O
F_{E SR} =
--------------------¹---------------------
2π × ESR × C_O
The compensation network consists of the error amplifier
(internal to the ISL6432) and the impedance networks Z_IN
and Z_FB. The goal of the compensation network is to provide
a closed loop transfer function with high 0dB crossing
frequency (f_0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f_0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 6. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1^ST Zero Below Filter’s Double Pole (~75% F_LC)
3. Place 2^ND Zero at Filter’s Double Pole
4. Place 1^ST Pole at the ESR Zero
5. Place 2^ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
F_Z1
=
-----------------¹------------------
2π × R2 × C1
F_Z2
=
----------------------------¹-----------------------------
2π × (R_S1 + R3) × C3
F_P1
=
---------------------------¹---------------------------
2π
×
R₂
×


CC_-----1-1_----+×_-----CC_-----22_{- }
F_P2 = ₂----_π-----_×-----_R---¹--₃-----_×-----_C----₃--
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 6. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F_P2 with the capabilities
of the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 10 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
ACPI Implementation
The three linear controllers included within the ISL6432 can
independently be shut down, in order to accommodate
Advanced Configuration and Power Interface (ACPI) power
management features.
To shut down any of the linears, one needs to pull and keep
high the respective FB pin above a typical threshold of 1.25V.
One way to achieve this task is by using a logic gate coupled
through a small-signal diode. The diode should be placed as
close to the FB pin as possible to minimize stray capacitance
to this pin. Upon turn-off of the pull-up device, the respective
output undergoes a soft-start cycle, bringing the output within
regulation limits. On the regulators implementing this feature,
the parallel combination of the feedback resistors has to be
sufficiently high to allow ease of driving from the external
device. Considering the other restriction applying to the upper
range of this resistor combination (see ‘Output Voltage
Selection’ paragraph), it is recommended the values of the
feedback resistors on an ACPI-enabled linear regulator output
meet the following constraint:
2k Ω < -^R----^S-----^×-----^R-----^P- < 5k Ω
R_S + R_P
To turn off the switching regulator, use an open-drain or
open-collector device capable of pulling the OCSET pin (with
the attached R_OCSET pull-up) below 1.25V. To minimize the
possibility of OC trips at levels different than predicted, a
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