ISL6432 Datasheet, PDF (6/12 Pages) Intersil Corporation – PWM and Triple Linear Power Controller for Home Gateway Applications

ISL6432
three-cycle wait, the fourth soft-start initiates a ramp-up
attempt of the failed output, at time T2, bringing the output in
regulation at time T4.
To exemplify an UV event on one of the linears, at time T1,
the clock regulator (V_OUT2) is also subjected to an
overcurrent event, resulting in an UV condition. Similarly,
after three soft-start periods, the fourth cycle initiates a
ramp-up of this linear output at time T3. One soft-start period
after T3, the linear output is within regulation limits. UV
glitches less than 1µs (typically) in duration are ignored.
(0.5V/DIV.)
0V
UV MONITORING
V_OUT3 (1.8V)
V_OUT4 (1.5V)
V_OUT2 (2.5V)
V_OUT1 (2.5V)
ACTIVE
SOFT-START
FUNCTION
INACTIVE
T0
T1
TIME
T2
T3 T4
FIGURE 1. OVERCURRENT/UNDERVOLTAGE PROTECTION
RESPONSE
As overcurrent protection is performed on the synchronous
switcher regulator on a cycle-by-cycle basis, OC monitoring
is active as long as the regulator is operational. Since the
overcurrent protection on the linear regulators is performed
through undervoltage monitoring at the feedback pins (FB2,
FB3, and FB4), this feature is activated approximately 25%
into the soft-start interval (see Figure 1).
A resistor (R_OCSET) programs the overcurrent trip level for
the PWM converter. As shown in Figure 2, the internal
40µA current sink (I_OCSET) develops a voltage across
R_OCSET (V_SET) that is referenced to V_IN . The DRIVE
signal enables the overcurrent comparator (OCC). When
the voltage across the upper MOSFET (V_DS(ON)) exceeds
V_SET, the overcurrent comparator trips to set the
overcurrent latch. Both V_SET and V_DS(ON) are referenced
to V_IN and a small capacitor across R_OCSET helps V_OCSET
track the variations of V_IN due to MOSFET switching. The
overcurrent function will trip at a peak inductor current
(I_PEAK) determined by:
I_PEAK
=
I---_{O----C----S----E----T-----}×_{-----R----O-----C----S----E---T--}
r_DS(ON)
The OC trip point varies with MOSFET’s r_DS(ON)
temperature variations. To avoid overcurrent tripping in the
normal operating load range, determine the R_OCSET
resistor from the equation above with:
1. The maximum r_DS(ON) at the highest junction temperature.
2. The minimum I_OCSET from the specification table.
3. Determine I_PEAK for I_PEAK > I_OUT(MAX) + (∆I) /2, where
∆I is the output inductor ripple current.
OVERCURRENT TRIP:
VDS > VSET
iD × rDS_(ON) > IOCSET × ROCSET
OCSET
V_IN = +5V
R_OCSET
I_OCSET
40µA
DRIVE
V_SET +
VCC
UGATE
i_D
+
V_DS(ON)
OC
+
-
OCC
PWM
GATE
CONTROL
PHASE
VPHASE = VIN – VDS
VOCSET = VIN – VSET
FIGURE 2. OVERCURRENT DETECTION
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
+3.3V_IN
V_OUT3
+
C_OUT3
Q4
DRIVE3
FB3
R_S3
R_P3
Q5
V_OUT4
+
C_OUT4
DRIVE4
R_S4
FB4
R_P4
ISL6432
V_OUT
=
0.8
×

1

+
R^-R----SP--_{}
FIGURE 3. ADJUSTING THE OUTPUT VOLTAGE OF ANY OF
THE FOUR REGULATORS (OUTPUTS 3 AND 4
PICTURED)
Output Voltage Selection
The output voltage of the PWM converter can be resistor-
programmed to any level between V_IN and 0.8V. However,
since the value of R_S1 is affecting the values of the rest of
the compensation components, it is advisable its value is
kept between 2kΩ and 5kΩ.
All linear regulators’ output voltages are set by means of
external resistor dividers as shown in Figure 3. The two
resistors used to set the voltage on each of the three linear
regulators have to meet the following criteria: their value
while in a parallel connection has to be less than 5kΩ, or
otherwise said, the following relationship has to be met:
-^R----^S-----^×-----^R-----^P- < 5 kΩ
R_S + R_P
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