ISL6412_07 Datasheet, PDF (8/10 Pages) Intersil Corporation – Triple Output, Low-Noise LDO Regulator with Integrated Reset Circuit

ISL6412
pin also goes LOW during thermal shutdown or an
overcurrent event on LDO1. Connect this pin to GND, if
unused.
RESET - This pin is the active-LOW output of the push-pull
output stage of the integrated reset supervisory circuit. The
reset circuit monitors V_IN and asserts a RESET output at this
pin, if V_IN falls below the RESET threshold. The RESET
output remains LOW, while the V_IN pin voltage is below the
reset threshold, and for at least 25ms, after V_IN rises above
the RESET threshold.
Functional Description
The ISL6412 is a 3-in-1 multi-output, low dropout, regulator
designed for wireless chipset power applications. It supplies
three fixed output voltages 1.8V, 2.8V and 2.8V. Each LDO
consists of a 1.2V reference, error amplifier, MOSFET driver,
P-Channel pass transistor, dual-mode comparator and
internal feedback voltage divider.
The 1.2V band gap reference is connected to the error
amplifier’s inverting input. The error amplifier compares this
reference to the selected feedback voltage and amplifies the
difference. The MOSFET driver reads the error signal and
applies the appropriate drive to the P-Channel pass transistor.
If the feedback voltage is lower then the reference voltage, the
pass transistor gate is pulled lower, allowing more current to
pass and increasing the output voltage. If the feedback
voltage is higher then the reference voltage, the pass
transistor gate is driven higher, allowing less current to pass to
the output. The output voltage is fed back through an internal
resistor divider connected to OUT1/OUT2/OUT3 pins.
Additional blocks include an output overcurrent protection,
thermal sensor, fault detector, RESET function and
shutdown logic.
Internal P-Channel Pass Transistors
The ISL6412 features a typical 0.5Ω r_DS(ON) P-channel
MOSFET pass transistors. This provides several advantages
over similar designs using PNP bipolar pass transistors. The
P-Channel MOSFET requires no base drive, which reduces
quiescent current considerably. PNP based regulators waste
considerable current in dropout when the pass transistor
saturates. They also use high base drive currents under
large loads. The ISL6412 does not suffer from these
problems.
Integrated Reset for MAC/Baseband Processors
The ISL6412 includes a microprocessor supervisory block.
This block eliminates the extra reset IC and external
components needed in wireless chipset applications. This
block performs a single function; it asserts a RESET signal
whenever the V_IN supply voltage decreases below a preset
threshold, keeping it asserted for a programmable time (set
by external capacitor CT) after the V_IN pin voltage has risen
above the reset threshold. The reset threshold for the
ISL6412 is 2.63V typical.
The voltage at the CT pin is compared to the 1.2V bandgap
voltage. The charging of the CT capacitor behaves like an
RC network and the RESET delay can be approximated by:
Td = -R*C*ln(1-1.2V/VIN)
Where C is the capacitor at CT, and R is 11.1MΩ for
VIN = 3.3V. With no capacitor on the CT pin the RESET
delay will be close to zero. Figure 12 shows the RESET
delay vs CT capacitance.
500
400
300
200
100
0
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0
CT (µF)
FIGURE 12. RESET DELAY vs CT CAPACITANCE
Output Voltages
The ISL6412 provides fixed output voltages for use in
Wireless Chipset applications. Internal trimmed resistor
networks set the typical output voltages as shown here:
V_OUT1 = 1.8V; V_OUT2 = 2.8V; V_OUT3 = 2.8V.
Shutdown
Pulling the SHDN pin LOW puts the complete chip into
shutdown mode, and supply current drops to 5μA typical.
This input has an internal pull-up resistor, so that in normal
operation the outputs are always enabled; external pull-up
resistors are not required.
Current Limit
The ISL6412 monitors and controls the pass transistor’s
gate voltage to limit the output current. The current limit for
LDO1 is 500mA, LDO2 is 330mA and LDO3 is 300mA. The
output can be shorted to ground without damaging the part
due to the current limit and thermal protection features.
8
FN9067.1
March 20, 2007