ISL6412_07 Datasheet, PDF (5/10 Pages) Intersil Corporation – Triple Output, Low-Noise LDO Regulator with Integrated Reset Circuit

ISL6412
Electrical Specifications V_IN = +3.3V, Compensation Capacitor = 33nF, T_A = +25°C, unless otherwise noted. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage Noise (Note 7)
LDO3 SPECIFICATIONS
10Hz < f < 100kHz, I_OUT = 10mA
C_OUT = 2.2μF
-
65
-
μV_RMS
C_OUT = 10μF
-
60
-
μV_RMS
Output Voltage (V_OUT3)
Output Voltage Accuracy
Maximum Output Current (I_OUT3) (Note 7)
Output Current Limit (Note 7)
-
2.8
-
V
I_OUT = 10mA, T_A = -40°C to +85°C
-2.0
-
2.0
%
V_IN = 3.6V
225
-
-
mA
300
450
840
mA
Dropout Voltage (Notes 5, 7)
Line Regulation
Load Regulation
Output Voltage Noise (Note 7)
RESET BLOCK SPECIFICATIONS
I_OUT = 125mA
-
100
160
mV
V_IN = 3.0V to 3.6V, I_OUT = 10mA
-0.15
0.0
0.15
%/V
I_OUT = 10mA to 125mA
-
0.2
1.0
%
10Hz < f < 100kHz, I_OUT = 10mA
C_OUT = 2.2μF
-
30
-
μV_RMS
C_OUT = 10μF
-
20
-
μV_RMS
Reset Threshold
2.564
2.630
2.66
V
Reset Threshold Hysteresis (Note 7)
6.3
-
-
mV
V_IN to Reset Delay
RESET Active Timeout Period (Notes 6, 7)
VCC = V_TH to V_TH - 100mV
CT = 0.01µF
-
20
-
μs
50
-
-
ms
FAULT1
Rising Threshold
% of V_OUT
+5.5
+8.0
+10.5
%
Falling Threshold
% of V_OUT
-10.5
-8.0
-5.5
%
NOTES:
5. The dropout voltage is defined as V_IN - V_OUT, when V_OUT is 50mV below the value of V_OUT for V_IN = V_OUT + 0.5V.
6. The RESET time is linear with CT at a slope of ~5ms/nF. Thus, at 10nF (0.01μF) the RESET time is 50ms.
7. Guaranteed by design, not production tested.
Typical Performance Curves
The test conditions for the Typical Operating Performance are: V_IN = 3.3V, T_A = +25°C,
Unless Otherwise Noted
SHDN
1V/DIV
VOUT3
1V/DIV
VOUT2
1V/DIV
VOUT1
1V/DIV
100µs/DIV
FIGURE 1. START-UP SEQUENCE
5
SHDN
1V/DIV
VOUT1
1V/DIV
100µs/DIV
VOUT2
1V/DIV
VOUT3
1V/DIV
FIGURE 2. SHUTDOWN SEQUENCE
FN9067.1
March 20, 2007