ISL6208A Datasheet, PDF (8/10 Pages) Intersil Corporation – High Voltage Synchronous Rectified Buck MOSFET Driver

ISL6208A
The equation can be rewritten to solve for R_DELAY as
follows:
R_DELAY(kΩ)
=
(_---T_{----D----E----L---A----Y----(--n---s----)---–----}5_----n_----s_----)
0.045
Internal Bootstrap Diode
This driver features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit.
The bootstrap capacitor must have a maximum voltage rating
above the maximum battery voltage plus 5V. The bootstrap
capacitor can be chosen from the following equation:
C_BO
O
T
≥
---^Q----^G-----^A----^T---^E----
∆V_BOOT
(EQ. 1)
where Q_GATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The ∆V_BOOT term is
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate
charge, Q_GATE, of 25nC at 5V and also assume the droop in
the drive voltage over a PWM cycle is 200mV. One will find
that a bootstrap capacitance of at least 0.125µF is required.
The next larger standard value capacitance is 0.15µF. A
good quality ceramic capacitor is recommended.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
Q_GATE = 100nC
0.4
0.2 _20nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
∆V_{BOOT_CAP} (V)
FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
will push the IC beyond the maximum recommended
operating junction temperature of 125°C. The maximum
allowable IC power dissipation for the SO-8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
P = f_sw(1.5V_UQ_U + V_LQ_L) + I_VCCV_CC
(EQ. 2)
where f_sw is the switching frequency of the PWM signal. V_U
and V_L represent the upper and lower gate rail voltage. Q_U
and Q_L is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The lV_CC V_CC product is the quiescent power
of the driver and is typically negligible.
1000
900
800
Q_U = 100nC
Q_L = 200nC
Q_U = 50nC
Q_L = 100nC
Q_U = 50nC
Q_L= 50nC
700
600
Q_U = 20nC
Q_L= 50nC
500
400
300
200
100
0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
FREQUENCY (kHz)
FIGURE 11. POWER DISSIPATION vs FREQUENCY
8
FN9272.0
February 15, 2006