ISL43L210 Datasheet, PDF (8/12 Pages) Intersil Corporation – Ultra Low ON-Resistance, +1.1V to +4.5V Single Supply, SPDT Analog Switch

ISL43L210
Test Circuits and Waveforms (Continued)
V+
C
50Ω
NO or NC
COM
IN₁
0V or V+
ANALYZER
R_L
NC or NO
GND
SIGNAL
GENERATOR
IMPEDANCE
ANALYZER
NO or NC
V+
C
IN 0V or V+
COM
GND
FIGURE 6. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL43L210 is a bidirectional, single pole/double throw
(SPDT) analog switch that offers precise switching capability
from a single +1.1V to +4.5V supply with low on-resistance
(0.34Ω) and high speed operation (t_ON = 7ns, t_OFF = 3ns). The
device is especially well suited for portable battery powered
equipment due to its low operating supply voltage (1.1V), low
power consumption (1.8µW max), low leakage currents
(100nA max), and the tiny SC70 packaging. The ultra low on-
resistance and Ron flatness provide very low insertion loss
and distortion to application that require signal reproduction.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can be protected by adding a 1kΩ resistor in
series with the input (see Figure 8). The resistor limits the
input current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
8
FIGURE 7. CAPACITANCE TEST CIRCUIT
purpose of using a low R_ON switch. Connecting schottky
diodes to the signal pins as shown in Figure 8 will shunt the
fault current to the supply or to ground thereby protecting the
switch. These schottky diodes must be sized to handle the
expected fault current.
OPTIONAL
SCHOTTKY
DIODE
OPTIONAL
PROTECTION
RESISTOR
V+
IN_X
V_NX
V_COM
OPTIONAL
SCHOTTKY
DIODE
GND
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL43L210 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL43L210 4.7V
maximum supply voltage provides plenty of room for the
10% tolerance of 4.2V supplies, as well as room for
overshoot and noise spikes.
The minimum recommended supply voltage is 1.1V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer
to the electrical specification tables and Typical Performance
curves for details.
FN6131.0
March 15, 2005