ISL3034E Datasheet, PDF (8/16 Pages) Intersil Corporation – 4-Channel And 6-Channel High Speed, Auto-direction Sensing Logic Level Translators

ISL3034E, ISL3035E, ISL3036E
Application Information
Overview
The ISL3034E, ISL3035E, ISL3036E are 100Mbps,
bi-directional voltage level translating ICs for multi-supply
voltage systems. These products shift lower voltage levels
on one interface side (supplied by V_L) to a higher voltage
level on the other interface side (supplied by V_CC), or vice
versa. V_OH of the I/OV_L pins tracks the V_L supply, while V_OH
of the I/OV_CC pins tracks the V_CC supply.
These ICs feature bit-by-bit auto-direction sensing to
increase flexibility, and to eliminate the need for direction
control pins. On chip pull-up current sources in the active
mode, and pull-up resistors in SHDN mode, eliminate the
need for most external bus resistors. Drivers interfacing with
these level translators may be open-drain or push-pull types,
and all three versions may also be used for unidirectional
level shifting.
The three versions share the same architecture, but the
ISL3034E is a general purpose 6-Channel version, while the
6-Channel ISL3035E specifically targets SD Card and other
memory card applications. The 4-channel ISL3036 targets
nibble and byte based applications, as well as 4-wire SPI
interfaces. Power supply ranges allow level shifting between
1.5V, 1.8V, and 2.5V powered devices on the V_L side to
2.5V, and 3.3V devices on the V_CC side.
Principles of Operation
When enabled, these level shifters detect transitions on an
I/O pin, and drive the appropriate logic level on the
corresponding I/O pin on the other “side”. If the transition
was low-to-high, the channel shifts the voltage up to V_CC (for
transitions on an I/OV_L pin) or down to V_L (for transitions on
an I/OV_CC pin), and then drives the shifted level on the other
side. The ISL3035E enables whenever V_CC > V_L + 200mV,
while the ISL3034E and ISL3036E enable if EN = 1 AND
V_CC > V_L + 200mV.
Upon detecting a transition on either I/O pin, that channel’s
accelerator circuitry actively drives the opposite side’s
(output) pin to GND or the output’s supply rail, and then turns
off. Weak hold circuitry then maintains the logic state until
the input is 3-stated, or until another active transition occurs
on either I/O pin for that channel. Figure 5 shows the
simplified block diagram of one level shifting channel. The
accelerator circuitry comprises high and low threshold
detectors, one shots with level shifters and large output
drivers. A transition on one of the I/OV_L or I/OV_CC pins
momentarily defines that pin as an input. When the high or
low threshold is crossed, a one-shot fires either the PMOS or
NMOS driver, respectively, on the opposite side (effectively
the output). These drivers are large enough to quickly drive
the output node to its respective supply or to GND. Note that
this transition on the “output” trips the transition detector on
that pin, firing its accelerator, which feeds back to the “input”
to help reinforce slow transitions, such as those from an
V_L
V_L
#
HIGH V_TH
DETECT
#
LOW V_TH
DETECT
V_CC
EN
I/OV_L
HIGH V_TH
#
DETECT
V_CC
LOW V_TH
DETECT
#
# ONE-SHOT AND LEVEL SHIFTER
I/OV_CC
FIGURE 5. ONE CHANNEL SIMPLIFIED SCHEMATIC
open-drain type driver. Once the one-shot - and thus the
accelerator - times out (approximately 3ns to 4ns), the large
output drivers tri-state and the pins are weakly held in the
last state by the small NMOS transistor between I/OV_L and
I/OV_CC (for a low) or by the small current sources (for a
high). In this static state, the I/O pins are easily overdriven by
the next transition from an external driver. Having large
pull-up and pull-down devices in the accelerator (vs just an
active pull-up) nearly eliminates the concern about the
external driver’s output impedance, and that impedance’s
effect on V_OL, fall times and data rate.
The weak pull-up current sources on each I/O pin and the
NMOS pass transistors, remain ON whenever the IC is
enabled. If a channel’s external driver tri-states, the weak
pull-up currents either keep the I/O pins high, or if the last
state was a low the current sources pull the I/O pins high. In
the latter case, each channel’s accelerators will once again
fire when either the I/OV_L or the I/OV_CC voltage crosses the
accelerator’s high threshold level.
Auto Direction Sensing
Each level translator channel independently and
automatically determines the direction of data transfer
without any external control signals. As described earlier, a
transition on either of the channel’s I/O pins momentarily
defines that pin as an input, which then translates and drives
that input signal to the channel’s corresponding pin on the
other port (now the output). After a brief period of active
driving, both I/O pins return to their weak “hold” mode, where
the next transition on either I/O pin determines the direction
for the next transfer.
Auto sensing saves valuable processor GPIO pins (three
[CLK, CMD, DAT] for SD Card applications, or six for the
general purpose hex case), and simplifies the software
associated with the peripheral interface.
Using Open Drain Drivers
These level translators’ accelerator based architecture
works equally well when driven by push-pull or open drain
type drivers (e.g., for the CMD line initialization in MMC
8
FN6492.0
March 31, 2009