ISL3034E Datasheet, PDF (10/16 Pages) Intersil Corporation – 4-Channel And 6-Channel High Speed, Auto-direction Sensing Logic Level Translators

ISL3034E, ISL3035E, ISL3036E
Best-in-Class ESD Protection
All pins on these devices include class 3 (>12kV) Human
Body Model (HBM) ESD protection structures, but the input
and I/O pins incorporate advanced structures allowing
them to survive ESD events in excess of ±15kV HBM and
±15kV to IEC61000-4-2. The I/OV_CC pins are particularly
vulnerable to ESD damage because they typically connect
to an exposed port on the exterior of the finished product.
Simply touching the port pins, or connecting a memory
card, can cause an ESD event that might destroy
unprotected ICs. These new ESD structures protect the
device whether or not it is powered up and without
degrading the level shifting performance. This built-in ESD
protection eliminates the need for board level protection
structures (e.g., transient suppression diodes) and the
associated, undesirable capacitive load they present. To
ensure the full benefit of the built-in ESD protection,
connect the IC’s GND pin directly to a low impedance GND
plane.
IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (typically I/OV_CC pins in memory card
applications) but the ISL3034E, ISL3035E, and ISL3036E
feature IEC61000 ESD protection on all logic and I/O pins
(both I/OV_L and I/OV_CC, as well as CLK pins). Unlike HBM
and MM methods which only test each pin-to-pin
combination without applying power, IEC61000 testing is
also performed with the IC in its typical application
configuration (power applied). The IEC61000 standard’s
lower current limiting resistor coupled with the larger charge
storage capacitor yields a test that is much more severe than
the HBM test. The extra ESD protection built into these
devices’ pins allows the design of equipment meeting level 4
criteria without the need for additional board level protection.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
repeatable results. All the EN, CLK, and I/O pins withstand
±15kV air-gap discharges, relative to GND.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages
higher than ±9kV. Devices in this family survive ±9kV contact
discharges (relative to the GND pin) on the EN, CLK, and I/O
pins.
Layout and Decoupling Considerations
These level translators’ high data rates and fast signal
transitions require that the accelerators have high transient
currents. Thus, short, low inductance supply traces and
decoupling within 1/8th inch of the IC are imperative with
very low impedance GND return paths.
Typical Performance Curves
V_CC = 3.3V, V_L = 1.8V, C_L = 15pF, R_SOURCE = 150Ω, Data Rate = 100Mbps, push-pull driver,
T_A = +25°C; Unless Otherwise Specified.
2.5
25
V_L = 1.8V
V_CC = 3.6V
SWITCHING 6 I/OV_L INPUTS
2.0
20
1.5
SWITCHING 4 I/OV_L INPUTS
SWITCHING 6 I/OV_CC INPUTS
15
1.0
SWITCHING 1 I/OV_L INPUT
0.5
0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
V_CC SUPPLY VOLTAGE (V)
FIGURE 7. V_L SUPPLY CURRENT vs V_CC SUPPLY VOLTAGE
10
SWITCHING 4 I/OV_CC INPUTS
5
SWITCHING 1 I/OV_CC INPUT
0
1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.2
V_L SUPPLY VOLTAGE (V)
FIGURE 8. V_L SUPPLY CURRENT vs V_L SUPPLY VOLTAGE
10
FN6492.0
March 31, 2009