ISL29034_14 Datasheet, PDF (8/15 Pages) Intersil Corporation – Integrated Digital Light Sensor

ISL29034
(LOW) on the SDA line (refer to Figure 11).
1
0
0
0
1
0
0
R/W
DEVICE ADDRESS
BYTE
A7
A6
A5
A4
A3
A2
A1
A0
REGISTER
ADDRESS BYTE
D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE
FIGURE 9. DEVICE ADDRESS, REGISTER ADDRESS, AND DATA BYTE
Write Operation
BYTE WRITE
In a byte write operation, the ISL29034 requires the Device
Address byte, Register Address byte, and the Data byte. The
master starts the communication with a START condition. Upon
receipt of the Device Address byte, Register Address byte, and
the Data byte, the ISL29034 responds with an acknowledge
(ACK). Following the ISL29034 data acknowledge response, the
master terminates the transfer by generating a STOP condition.
The ISL29034 then begins an internal write cycle of the data to
the volatile memory. During the internal write cycle, the device
inputs are disabled and the SDA line is in a high impedance state,
so the device will not respond to any requests from the master
(refer to Figure 10).
BURST WRITE
The ISL29034 has a burst write operation, which allows the
master to write multiple consecutive bytes from a specific
address location. It is initiated in the same manner as the byte
write operation, but instead of terminating the write cycle after
the first Data byte is transferred, the master can write to the
whole register array. After the receipt of each byte, the ISL29034
responds with an acknowledge, and the address is internally
incremented by one. The address pointer remains at the last
address byte written. When the counter reaches the end of the
register address list, it “rolls over” and goes back to the first
Register Address.
SIGNAL FROM
MASTER DEVICE
SIGNAL AT SDA
SIGNALS FROM
SLAVE DEVICE
S
T
A
DEVICE ADDRESS
BYTE
R
T
10001000
ADDRESS BYTE
A
A
C
C
K
K
DATA BYTE
S
T
O
P
A
C
K
FIGURE 10. BYTE WRITE SEQUENCE
SCL FROM
MASTER
SDA FROM
TRANSMITTER
SDA FROM
RECEIVER
8^th CLK
9^th CLK
HIGH
IMPEDANCE
START
DATA
DATA
DATA
STABLE ^CHANGE STABLE
ACK
FIGURE 11. START, DATA STABLE, ACKNOWLEDGE, AND STOP CONDITION
STOP
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8
FN8370.1
April 9, 2014