ISL29028IROZ Datasheet, PDF (8/16 Pages) Intersil Corporation – Low Power Ambient Light and Proximity Sensor with Intelligent Interrupt and Sleep Modes

ISL29028
BIT #
7:0
TABLE 10. REGISTER 0x08 (PROX_DATA) - PROXIMITY SENSOR DATA
ACCESS DEFAULT
BIT NAME
FUNCTION/OPERATION
RO
0x00
PROX_DATA
(Proximity Data)
Results of 8-bit proximity sensor ADC conversion
BIT #
7:0
TABLE 11. REGISTER 0x09 (ALSIR_DT1) - ALS/IR SENSOR DATA (LOWER 8 BITS)
ACCESS DEFAULT
BIT NAME
FUNCTION/OPERATION
RO
0x00
ALSIR_DATA
(ALS/IR Data)
Lower 8 bits (of 12 bits) from result of ALS/IR sensor conversion
BIT #
7:4
3:0
BIT #
7:0
BIT #
7:0
TABLE 12. REGISTER 0x0A (ALSIR_DT2) - ALS/IR SENSOR DATA (UPPER 4 BITS)
ACCESS DEFAULT
BIT NAME
FUNCTION/OPERATION
RO
0x00
(Unused)
Unused bits.
RO
0x00
ALSIR_DATA
(ALS/IR Data)
Upper 4 bits (of 12 bits) from result of ALS/IR sensor conversion
ACCESS
RW
TABLE 13. REGISTER 0x0E (TEST1) - TEST MODE
DEFAULT
BIT NAME
FUNCTION/OPERATION
0x00
(Write as 0x00) Test mode register. When 0x00, in normal operation.
ACCESS
RW
TABLE 14. REGISTER 0x0F (TEST2) - TEST MODE 2
DEFAULT
BIT NAME
FUNCTION/OPERATION
0x00
(Write as 0x00) Test mode register. When 0x00, in normal operation.
I²C DATA ^START
DEVICE ADDRESS W A REGISTER ADDRESS
STOP START DEVICE ADDRESS
A
DATA BYTE0
I²C SDA
MASTER
I²C SDA
SLAVE (ISL29028)
A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A
SDA DRIVEN BY MASTER
A SDA DRIVEN BY MASTER A
A6 A5 A4 A3 A2 A1 A0 W A
SDA DRIVEN BY ISL29028
SDA DRIVEN BY MASTER
A D7 D6 D5 D4 D3 D2 D1 D0
I²C CLK
12 3456 789123456 789
123 45 67 89123456789
FIGURE 2. I²C DRIVER TIMING DIAGRAM FOR MASTER AND SLAVE CONNECTED TO COMMON BUS
Principles of Operation
I²C Interface
The ISL29028’s I²C interface slave address is internally
hardwired as 0b100010<x>, where “0b” signifies binary
notation and x represents the logic level on pin ADDR0.
Figure 2 shows a sample one-byte read. The I²C bus
master always drives the SCL (clock) line, while either
the master or the slave can drive the SDA (data) line.
Every I²C transaction begins with the master asserting a
start condition (SDA falling while SCL remains high). The
first transmitted byte is initiated by the master and
includes 7 address bits and a R/W bit. The slave is
responsible for pulling SDA low during the ACK bit after
every transmitted byte.
Each I²C transaction ends with the master asserting a
stop condition (SDA rising while SCL remains high).
For more information about the I²C standard, please
consult the Philips^™ I²C specification documents.
Photodiodes and ADCs
The ISL29028 contains two photodiode arrays which
convert photons (light) into current. The ALS
photodiodes are constructed to mimic the human eye’s
wavelength response curve to visible light (see Figure 6).
The ALS photodiodes’ current output is digitized by a
12-bit ADC in 100ms. These 12 bits can be accessed by
reading from I²C registers 0x9 and 0xA when the ADC
conversion is completed.
The ALS converter is a charge-balancing integrating
12-bit ADC. Charge-balancing is best for converting small
current signals in the presence of periodic AC noise.
Integrating over 100ms highly rejects both 50Hz and
60Hz light flicker by picking the lowest integer number of
cycles for both 50Hz/60Hz frequencies.
8
FN6780.2
November 4, 2011