HI3304_02 Datasheet, PDF (8/12 Pages) Intersil Corporation – 4-Bit, 25 MSPS, Flash A/D Converter

HI3304
TABLE 1. OUTPUT CODE TABLE
INPUT VOLTAGE (V)
OUTPUT CODE
CODE
DESCRIPTION
Zero
V_REF+ = 1V 1.6V
2V
3.2V 4.8V
DECIMAL
V_REF- = -1V
0V
0V
0V
0V
OF B4 B3 B2 B1 COUNT
-1.000
0
0
0
0
0
0
0
0
0
0
1 LSB
-0.875
0.1
0.125
0.2
0.3
0
0
0
0
1
1
2 LSB
-0.750
0.2
0.250
0.4
0.6
0
0
0
1
0
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1_{/2 Full Scale -1 LSB}
-0.125
0.7
0.875
1.4
2.1
0
0
1
1
1
7
1_{/2 Full Scale}
0
0.8
1.000
1.6
2.4
0
1
0
0
0
8
1_{/2 Full Scale +1 LSB}
0.125
0.9
1.125
1.8
2.7
0
1
0
0
1
9
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Full Scale -1 LSB
0.750
1.4
1.750
2.8
4.2
0
1
1
1
0
14
Full Scale
0.875
1.5
1.875
3.0
4.5
0
1
1
1
1
15
Overflow
1.000
1.6
2.000
3.2
4.8
1
1
1
1
1
31
Step Size
0.125
0.1
0.125
0.2
0.3
NOTE:
1. The voltages listed are the ideal centers of each output code shown as a function of its associated reference voltage. See Ideal Transfer
Curve Figure 6. The output code should exist for an input equal to the ideal center voltage ±¹/₂ of the step size.
Description
Device Operation
A sequential parallel technique is used by the HI3304
converter to obtain its high speed operation. The sequence
consists of the “Auto Balance” phase and the “Sample
Unknown” phase (Refer to the circuit diagram). Each
conversion takes one clock cycle (see Note). The “Auto
Balance” (φ1) occurs during the Low period of the clock
cycle, and the “Sample Unknown” (φ2) occurs during the
High period of the clock cycle.
NOTE: This device requires only a single-phase clock. The terminology
of φ1 and φ2 refers to the High and Low periods of the same clock.
During the “Auto Balance” phase, a transmission-gate switch
is used to connect each of 16 commutating capacitors to
their associated ladder reference tap. Those tap voltages will
be as follows:
V_TAP(N) = [(V_REF/16) x N] - [V_REF/(2 x 16)]
= V_REF [(2N - 1)/32]
Where: V_TAP(N) = Reference ladder tap voltage at point N.
V_REF = Voltage across V_REF- to V_REF+
N = Tap number (1 through 16)
The other side of the capacitor is connected to a single-
stage inverting amplifier whose output is shorted to its input
by a switch. This biases the amplifier at its intrinsic trip point,
which is approximately (V_DD - V_SS)/2. The capacitors now
charge to their associated tap voltages, priming the circuit for
the next phase.
In the “Sample Unknown” phase, all ladder tap switches are
opened, the comparator amplifiers are no longer shorted,
and V_IN is switched to all 16 capacitors. Since the other end
of the capacitor is now looking into an effectively open cir-
cuit, any voltage that differs from the previous tap voltage will
appear as a voltage shift at the comparator amplifiers. All
comparators whose tap voltages were lower than V_IN will
drive the comparator outputs to a “low” state. All compara-
tors whose tap voltages were higher than V_IN will drive the
comparator outputs to a “high” state. A second, capacitor-
coupled, auto-zeroed amplifier further amplifies the outputs.
The status of all these comparator amplifiers are stored at the
end of this phase (φ2), by a secondary latching amplifier stage.
Once latched, the status of the 16 comparators is decoded by
a 16 to 5 bit decode array and the results are clocked into a
storage register at the rising edge of the next φ2.
If the input is greater than 31/32 x V_REF, the overflow output
will go “high”. (The bit outputs will remain high). If the output
differs from that of the previous conversion, the data change
output will go “high”.
A three-state buffer is used at the output of the 7 storage
registers which are controlled by two chip-enable signals.
CE1 will independently disable B1 through B4 when it is in a
high state. CE2 will independently disable B1 through B4
and the OF and DC buffers when it is in the low state.
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