HI3304_02 Datasheet, PDF (11/12 Pages) Intersil Corporation – 4-Bit, 25 MSPS, Flash A/D Converter

HI3304
+FULL
SCALE
REF.
BUFFER
INPUT
+5V
1kΩ
ADJUST
CENTER
+5V
V_AA+ DC
NC
V_DD
OF
NC
V_REF+ B4
V_IN
B3
V_REF- B2
V_AA- _B1
V_SS CE1
CLK CE2
HI3304
CLK
V_AA+
V_DD
V_REF +
V_IN
V_REF -
V_AA-
V_SS
DC
OF
B4
B3
B2
B1
CE1
CE2
NC
+5V
HI3304
CLOCK
INPUT
B5 MSB
B4
B3
B2
B1
FIGURE 13. TYPICAL HI3304 5-BIT CONFIGURATION
OVERFLOW
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
V₀ V₁ V₂ V₃ V₄ V₅ V₆ V₇ V₈ V₉ V₁₀ V₁₁V₁₂ V₁₃ V₁₄ V₁₅ V₁₆
INPUT VOLTAGE
FIGURE 14. IDEAL TRANSFER CURVE
Definitions
Operating and Handling Considerations
Dynamic Performance Definitions
HANDLING
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the HI3304. A low distortion sine
wave is applied to the input, it is sampled, and the output is
stored in RAM. The data is then transformed into the fre-
quency domain with a 4096 point FFT and analyzed to evalu-
ate the dynamic performance of the A/D. The sine wave input
to the part is -0.5dB down from fullscale for all these tests.
Signal-to-Noise (SNR)
SNR is the measured RMS signal to RMS noise at a speci-
fied input and sampling frequency. The noise is the RMS
sum of all of the spectral components except the fundamen-
tal and the first five harmonics.
Signal-to-Noise + Distortion Ratio (SINAD)
SINAD is the measured RMS signal to RMS sum of all other
spectral components below the Nyquist frequency excluding DC.
Effective Number of Bits (ENOB)
The effective number of bits (ENOB) is derived from the
SINAD data. ENOB is calculated from:
ENOB = (SINAD - 1.76 + V_CORR)/6.02,
where: V_CORR = 0.5dB.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic com-
ponents to the RMS value of the measured input signal.
All inputs and outputs of CMOS devices have a network for
electrostatic protection during handling. Recommended han-
dling practices for CMOS devices are described in
lCAN-6525. “Guide to Better Handling and Operation of
CMOS Integrated Circuits.”
OPERATING
Operating Voltage
During operation near the maximum supply voltage limit, care
should be taken to avoid or suppress power supply turn-on
and turn-off transients, power supply ripple, or ground noise;
any of these conditions must not cause the power supply volt-
ages to exceed the absolute maximum rating.
Input Signals
To prevent damage to the input protection circuit, input signals
should never be greater than V_DD or V_AA+ nor less than V_SS
or V_AA- (depending upon which supply the protection network
is referenced. See Maximum Ratings). Input currents must not
exceed 20mA even when the power supply is off.
Unused Inputs
A connection must be provided at every input terminal. All
unused input terminals must be connected to either V_DD or
V_SS, whichever is appropriate.
Output Short Circuits
Shorting of outputs to any supply potential may damage
CMOS devices by exceeding the maximum device dissipation.
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