CD4071BMS Datasheet, PDF (8/10 Pages) Intersil Corporation – CMOS OR Gate

CD4071BMS, CD4072BMS, CD4075BMS
VDD
14
*
8 (5, 13)
*
2 (4, 12)
*
1 (3, 11)
p
p
p
n
p
p
p
9 (6, 10)
n
n
n
n
p
n
n
p
n
n
VDD
VSS
7
VSS
* ^{ALL INPUTS PROTECTED BY}
CMOS PROTECTION NETWORK
FIGURE 5. SCHEMATIC DIAGRAM FOR CD4075BMS (1 OF 3 IDENTICAL GATES)
A
1 (3, 11)
B
2 (4, 12)
C
8 (5, 13)
J
9 (6, 10)
FIGURE 6. LOGIC DIAGRAM FOR CD4075BMS (1 OF 3 IDENTICAL GATES)
Typical Performance Characteristics
20
AMBIENT TEMPERATURE (T_A) = +25^oC
SUPPLY VOLTAGE (VDD) = 15V
15
10V
10
5V
5
200
AMBIENT TEMPERATURE (T_A) = +25^oC
150
SUPPLY VOLTAGE (VDD) = 5V
100
50 _10V
15V
0
5
10
15
20
INPUT VOLTAGE (VIN) (V)
FIGURE 7. TYPICAL VOLTAGE TRANSFER CHARACTERIS-
TICS
0
20
40
60
80
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
7-451