CD4071BMS Datasheet, PDF (7/10 Pages) Intersil Corporation – CMOS OR Gate

CD4071BMS, CD4072BMS, CD4075BMS
VDD
14
*
1 (6, 8, 13)
p
p
p
p
p
3 (4, 10, 11)
n
n
n
n
VDD
*
2 (5,9, 12)
p
n
VSS
n
7
VSS
* ^{ALL INPUTS PROTECTED BY}
CMOS PROTECTION NETWORK
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4071BMS (1 OF 4 IDENTICAL GATES)
B
1 (6, 8, 13)
J
A
2 (5, 9, 12)
3 (4, 10, 11)
*
2 (12)
FIGURE 2. LOGIC DIAGRAM FOR CD4071BMS (1 OF 4 IDENTICAL GATES)
INV.1**
p
VDD
p
n
VDD
p
n
n
VDD
p
p
n
VDD
p
1 (13)
n
n
VSS
*
3 (11)
*
5 (9)
*
4 (10)
INV 2**
INV 3**
INV 4**
VSS
VDD
p
p
n
n
VSS
VSS
VDD
VSS
VSS
** INVERTERS 2, 3 AND 4 ARE IDENTICAL TO INVERTER 1.
* ^{ALL INPUTS PROTECTED BY}
CMOS PROTECTION NETWORK
FIGURE 3. SCHEMATIC DIAGRAM FOR CD4072BMS (1 OF 2 IDENTICAL GATES)
A
2 (12)
B
3 (11)
D
5 (9)
J
1 (13)
C
4 (10)
FIGURE 4. LOGIC DIAGRAM FOR CD4072BMS (1 OF 2 IDENTICAL GATES)
7-450