CD4042BMS Datasheet, PDF (8/8 Pages) Intersil Corporation – CMOS Quad Clocked “D” Latch

CD4042BMS
Typical Performance Characteristics (Continued)
300
300
250
250
SUPPLY VOLTAGE (VDD) = 5V
SUPPLY VOLTAGE (VDD) = 5V
200
200
150
150
10V
10V
100
15V
100
15V
50
AMBIENT TEMPERATURE (T_A) = +25^oC
0
20 40 60 80 100 120 140
LOAD CAPACITANCE (CL) (pF)
FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE - CLOCK TO Q
50
AMBIENT TEMPERATURE (T_A) = +25^oC
0
20 40 60 80 100 120 140
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE - CLOCK TO Q
10⁶ _{AMBIENT TEMPERATURE (TA) = +25}o_C
10⁵
SUPPLY VOLTAGE (VDD) = 15V
10⁴
10³
10V
10V
10²
5V
10
1
10³
CL = 50pF
CL = 15pF
10⁴
10⁵
10⁶
10⁷
INPUT FREQUENCY (fI) (kHz)
FIGURE 9. TYPICAL POWER DISSIPATION vs FREQUENCY
CLOCK
CL
NOTE 1
NOTE 2
DATA
INPUT
D
LATCH
LOW DATA _{tS tH}
LATCH
HIGH DATA
Q
OUTPUT
LOW DATA
LATCHED
HIGH DATA
LATCHED
tPHL, tPLH
D TO Q OR Q
tPHL, tPLH
CL TO Q OR Q
NOTES:
1. For positive clock edge, input data is
latched when polarity is low.
2. For negative clock edge, input data is
latched when polarity is high.
FIGURE 11. DYNAMIC TEST PARAMETERS
AMBIENT TEMPERATURE (T_A) = +25^oC
200
SUPPLY VOLTAGE (VDD) = 5V
150
100
10V
15V
50
0
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 10. TYPICAL TRANSITION TIME vs LOAD CAPACI-
TANCE
Chip Dimensions and Pad Layout
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated
Grid graduations are in mils (10^-3 inch).
7-875